YGGverse/xash3d-fwgs
1
0
Fork 0
mirror of https://github.com/YGGverse/xash3d-fwgs.git synced 2025-01-11 07:37:52 +00:00
Code Issues Projects Releases Wiki Activity

public: build: add ARMv8 32-bit support, in case of someone actually uses it

Browse Source
This commit is contained in:
Alibek Omarov 2020-09-28 16:17:08 +03:00
parent 80a5c53cb2
commit 2aaa6c6e04
3 changed files with 14 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
engine/common/build.c
View File

@ -115,11 +115,13 @@ const char *Q_buildarch( void )
archname = "amd64"; archname = "amd64";
#elif XASH_X86 #elif XASH_X86
archname = "i386"; archname = "i386";
#elif XASH_ARM64 #elif XASH_ARM && XASH_64BIT
archname = "arm64"; archname = "arm64";
#elif XASH_ARM #elif XASH_ARM
archname = "armv" archname = "armv"
#if XASH_ARM == 7 #if XASH_ARM == 8
"8_32" // for those who (mis)using 32-bit OS on 64-bit CPU
#elif XASH_ARM == 7
"7" "7"
#elif XASH_ARM == 6 #elif XASH_ARM == 6
"6" "6"

2
engine/common/crashhandler.c
View File

@ -336,7 +336,7 @@ static void Sys_Crash( int signal, siginfo_t *si, void *context)
bp = (void**)ucontext->uc_mcontext.gregs[REG_EBP]; bp = (void**)ucontext->uc_mcontext.gregs[REG_EBP];
sp = (void**)ucontext->uc_mcontext.gregs[REG_ESP]; sp = (void**)ucontext->uc_mcontext.gregs[REG_ESP];
#endif #endif
#elif XASH_ARM64 #elif XASH_ARM && XASH_64BIT
pc = (void*)ucontext->uc_mcontext.pc; pc = (void*)ucontext->uc_mcontext.pc;
bp = (void*)ucontext->uc_mcontext.regs[29]; bp = (void*)ucontext->uc_mcontext.regs[29];
sp = (void*)ucontext->uc_mcontext.sp; sp = (void*)ucontext->uc_mcontext.sp;

17
public/build.h
View File

@ -45,13 +45,13 @@ For more information, please refer to <http://unlicense.org/>
#undef XASH_ANDROID #undef XASH_ANDROID
#undef XASH_APPLE #undef XASH_APPLE
#undef XASH_ARM #undef XASH_ARM
#undef XASH_ARM64
#undef XASH_ARM_HARDFP #undef XASH_ARM_HARDFP
#undef XASH_ARM_SOFTFP #undef XASH_ARM_SOFTFP
#undef XASH_ARMv4 #undef XASH_ARMv4
#undef XASH_ARMv5 #undef XASH_ARMv5
#undef XASH_ARMv6 #undef XASH_ARMv6
#undef XASH_ARMv7 #undef XASH_ARMv7
#undef XASH_ARMv8
//#undef XASH_BIG_ENDIAN //#undef XASH_BIG_ENDIAN
#undef XASH_BSD #undef XASH_BSD
#undef XASH_E2K #undef XASH_E2K
@ -169,14 +169,13 @@ For more information, please refer to <http://unlicense.org/>
#define XASH_AMD64 1 #define XASH_AMD64 1
#elif defined(__i386__) || defined(_X86_) || defined(_M_IX86) #elif defined(__i386__) || defined(_X86_) || defined(_M_IX86)
#define XASH_X86 1 #define XASH_X86 1
#elif defined __aarch64__ #elif defined __aarch64__ || defined _M_ARM64
#define XASH_64BIT 1 #define XASH_64BIT 1
#define XASH_ARM64 1 #define XASH_ARM 8
#elif defined __arm__ || defined _M_ARM #elif defined __arm__ || defined _M_ARM
#if defined _M_ARM #if __ARM_ARCH == 8 || __ARM_ARCH_8__
// msvc can only armv7 ? #define XASH_ARM 8
#define XASH_ARM 7 #elif __ARM_ARCH == 7 || __ARM_ARCH_7__ || defined _M_ARM // msvc can only armv7 in 32 bit
#elif __ARM_ARCH == 7 || __ARM_ARCH_7__
#define XASH_ARM 7 #define XASH_ARM 7
#elif __ARM_ARCH == 6 || __ARM_ARCH_6__ || __ARM_ARCH_6J__ #elif __ARM_ARCH == 6 || __ARM_ARCH_6__ || __ARM_ARCH_6J__
#define XASH_ARM 6 #define XASH_ARM 6
@ -212,7 +211,9 @@ For more information, please refer to <http://unlicense.org/>
#define XASH_64BIT 1 #define XASH_64BIT 1
#endif #endif
#if XASH_ARM == 7 #if XASH_ARM == 8
#define XASH_ARMv8 1
#elif XASH_ARM == 7
#define XASH_ARMv7 1 #define XASH_ARMv7 1
#elif XASH_ARM == 6 #elif XASH_ARM == 6
#define XASH_ARMv6 1 #define XASH_ARMv6 1