mirror of
https://github.com/GOSTSec/sgminer
synced 2025-01-22 20:44:19 +00:00
Create a separate thread for handling all work and idle submission to the avalon which messages the scanhash function it has completed to update statistics.
This commit is contained in:
Con Kolivas
parent
c87f4c303f
commit
629feb5f3f
267
driver-avalon.c
267
driver-avalon.c
@ -295,47 +295,6 @@ static void avalon_clear_readbuf(int fd)
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} while (ret > 0);
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}
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/* Wait until the avalon says it's ready to receive a write, or 2 seconds has
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* elapsed, whichever comes first. The status is updated by the ftdi device
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* every 40ms. Returns true if the avalon is ready. */
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static bool avalon_wait_write(int fd)
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{
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int i = 0;
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bool ret;
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do {
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ret = avalon_buffer_full(fd);
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if (ret)
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nmsleep(50);
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} while (ret == true && i++ < 40);
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return !ret;
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}
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static void avalon_idle(struct cgpu_info *avalon, int fd)
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{
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struct avalon_info *info = avalon->device_data;
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int i;
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for (i = 0; i < info->miner_count; i++) {
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struct avalon_task at;
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int ret;
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avalon_clear_readbuf(fd);
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if (unlikely(avalon_buffer_full(fd))) {
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applog(LOG_WARNING, "Avalon buffer full in avalon_idle after %d tasks", i);
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break;
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}
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avalon_init_task(&at, 0, 0, info->fan_pwm,
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info->timeout, info->asic_count,
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info->miner_count, 1, 1, info->frequency);
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ret = avalon_write(fd, (char *)&at, AVALON_WRITE_SIZE);
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if (unlikely(ret == AVA_SEND_ERROR))
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break;
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}
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applog(LOG_ERR, "Avalon: Going to idle mode");
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}
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static int avalon_reset(struct cgpu_info *avalon, int fd)
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{
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struct avalon_result ar;
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@ -344,20 +303,10 @@ static int avalon_reset(struct cgpu_info *avalon, int fd)
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int ret, i = 0;
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struct timespec p;
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/* Reset once, then send command to go idle */
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ret = avalon_write(fd, &reset, 1);
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if (unlikely(ret == AVA_SEND_ERROR))
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return -1;
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/* Ignore first result as it may be corrupt with old work */
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/* There's usually a one byte response after opening */
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avalon_clear_readbuf(fd);
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/* What do these sleeps do?? */
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p.tv_sec = 0;
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p.tv_nsec = AVALON_RESET_PITCH;
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nanosleep(&p, NULL);
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avalon_idle(avalon, fd);
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/* Reset again, then check result */
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/* Reset once, then send command to go idle */
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ret = avalon_write(fd, &reset, 1);
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if (unlikely(ret == AVA_SEND_ERROR))
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return -1;
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@ -377,16 +326,19 @@ static int avalon_reset(struct cgpu_info *avalon, int fd)
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}
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if (i != 11) {
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applog(LOG_ERR, "Avalon: Reset failed! not an Avalon?"
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" (%d: %02x %02x %02x %02x)",
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applog(LOG_ERR, "AVA%d: Reset failed! not an Avalon?"
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" (%d: %02x %02x %02x %02x)", avalon->device_id,
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i, buf[0], buf[1], buf[2], buf[3]);
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/* FIXME: return 1; */
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} else
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applog(LOG_WARNING, "Avalon: Reset succeeded");
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applog(LOG_WARNING, "AVA%d: Reset succeeded",
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avalon->device_id);
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/* What do these sleeps do?? */
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p.tv_sec = 0;
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p.tv_nsec = AVALON_RESET_PITCH;
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nanosleep(&p, NULL);
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avalon_idle(avalon, fd);
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if (!avalon_wait_write(fd))
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applog(LOG_WARNING, "Avalon: Not ready for writes?");
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return 0;
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}
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@ -693,7 +645,7 @@ static void *avalon_get_results(void *userdata)
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pthread_detach(pthread_self());
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snprintf(threadname, 24, "ava_getres/%d", avalon->device_id);
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snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
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RenameThread(threadname);
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while (42) {
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@ -739,6 +691,80 @@ static void *avalon_get_results(void *userdata)
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return NULL;
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}
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static void avalon_rotate_array(struct cgpu_info *avalon)
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{
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avalon->queued = 0;
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if (++avalon->work_array >= AVALON_ARRAY_SIZE)
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avalon->work_array = 0;
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}
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static void *avalon_send_tasks(void *userdata)
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{
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struct cgpu_info *avalon = (struct cgpu_info *)userdata;
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struct avalon_info *info = avalon->device_data;
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const int avalon_get_work_count = info->miner_count;
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int fd = avalon->device_fd;
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char threadname[24];
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bool idle = false;
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pthread_detach(pthread_self());
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snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
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RenameThread(threadname);
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while (42) {
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int start_count, end_count, i, j, ret;
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struct avalon_task at;
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int idled = 0;
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while (avalon_buffer_full(fd)) {
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nmsleep(40);
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}
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mutex_lock(&info->qlock);
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start_count = avalon->work_array * avalon_get_work_count;
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end_count = start_count + avalon_get_work_count;
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for (i = start_count, j = 0; i < end_count; i++, j++) {
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if (unlikely(avalon_buffer_full(fd))) {
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applog(LOG_WARNING,
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"AVA%i: Buffer full before all work queued",
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avalon->device_id);
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break;
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}
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if (likely(j < avalon->queued)) {
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idle = false;
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avalon_init_task(&at, 0, 0, info->fan_pwm,
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info->timeout, info->asic_count,
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info->miner_count, 1, 0, info->frequency);
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avalon_create_task(&at, avalon->works[i]);
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} else {
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idled++;
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avalon_init_task(&at, 0, 0, info->fan_pwm,
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info->timeout, info->asic_count,
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info->miner_count, 1, 1, info->frequency);
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}
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ret = avalon_send_task(fd, &at, avalon);
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if (unlikely(ret == AVA_SEND_ERROR)) {
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applog(LOG_ERR, "AVA%i: Comms error(buffer)",
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avalon->device_id);
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dev_error(avalon, REASON_DEV_COMMS_ERROR);
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avalon_reset(avalon, fd);
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}
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}
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pthread_cond_signal(&info->qcond);
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mutex_unlock(&info->qlock);
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if (unlikely(idled && !idle)) {
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idle = true;
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applog(LOG_WARNING, "AVA%i: Idled %d miners",
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avalon->device_id, idled);
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}
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avalon_rotate_array(avalon);
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}
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return NULL;
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}
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static bool avalon_prepare(struct thr_info *thr)
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{
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struct cgpu_info *avalon = thr->cgpu;
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@ -753,8 +779,15 @@ static bool avalon_prepare(struct thr_info *thr)
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info->thr = thr;
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mutex_init(&info->lock);
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mutex_init(&info->qlock);
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if (unlikely(pthread_cond_init(&info->qcond, NULL)))
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quit(1, "Failed to pthread_cond_init avalon qcond");
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avalon_clear_readbuf(avalon->device_fd);
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if (pthread_create(&info->write_thr, NULL, avalon_send_tasks, (void *)avalon))
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quit(1, "Failed to create avalon write_thr");
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if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
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quit(1, "Failed to create avalon read_thr");
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@ -875,112 +908,60 @@ static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *in
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static bool avalon_fill(struct cgpu_info *avalon)
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{
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int subid, slot, mc = avalon_infos[avalon->device_id]->miner_count;
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struct avalon_info *info = avalon->device_data;
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struct work *work;
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bool ret = true;
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mutex_lock(&info->qlock);
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if (avalon->queued >= mc)
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return true;
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goto out_unlock;
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work = get_queued(avalon);
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if (unlikely(!work))
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return false;
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if (unlikely(!work)) {
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ret = false;
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goto out_unlock;
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}
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subid = avalon->queued++;
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work->subid = subid;
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slot = avalon->work_array * mc + subid;
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if (likely(avalon->works[slot]))
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work_completed(avalon, avalon->works[slot]);
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avalon->works[slot] = work;
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if (avalon->queued >= mc)
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return true;
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return false;
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}
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if (avalon->queued < mc)
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ret = false;
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out_unlock:
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mutex_unlock(&info->qlock);
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static void avalon_rotate_array(struct cgpu_info *avalon)
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{
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avalon->queued = 0;
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if (++avalon->work_array >= AVALON_ARRAY_SIZE)
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avalon->work_array = 0;
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return ret;
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}
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static int64_t avalon_scanhash(struct thr_info *thr)
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{
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struct cgpu_info *avalon;
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struct work **works;
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int fd, ret = AVA_GETS_OK, full;
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struct cgpu_info *avalon = thr->cgpu;
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struct avalon_info *info = avalon->device_data;
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struct timeval now, then, tdiff;
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int64_t hash_count, us_timeout;
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struct timespec abstime;
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struct avalon_info *info;
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struct avalon_task at;
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int i;
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int avalon_get_work_count;
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int start_count, end_count;
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/* Full nonce range */
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us_timeout = 0x100000000ll / info->asic_count / info->frequency;
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tdiff.tv_sec = us_timeout / 1000000;
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tdiff.tv_usec = us_timeout - (tdiff.tv_sec * 1000000);
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cgtime(&now);
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timeradd(&now, &tdiff, &then);
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abstime.tv_sec = then.tv_sec;
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abstime.tv_nsec = then.tv_usec * 1000;
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struct timeval tv_start, elapsed;
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int64_t hash_count;
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static int first_try = 0;
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avalon = thr->cgpu;
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works = avalon->works;
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info = avalon->device_data;
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avalon_get_work_count = info->miner_count;
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fd = avalon->device_fd;
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#ifndef WIN32
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tcflush(fd, TCOFLUSH);
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#endif
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start_count = avalon->work_array * avalon_get_work_count;
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end_count = start_count + avalon_get_work_count;
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i = start_count;
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while (true) {
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avalon_init_task(&at, 0, 0, info->fan_pwm,
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info->timeout, info->asic_count,
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info->miner_count, 1, 0, info->frequency);
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avalon_create_task(&at, works[i]);
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ret = avalon_send_task(fd, &at, avalon);
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if (unlikely(ret == AVA_SEND_ERROR ||
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(ret == AVA_SEND_BUFFER_EMPTY &&
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(i + 1 == end_count) &&
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first_try))) {
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applog(LOG_ERR, "AVA%i: Comms error(buffer)",
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avalon->device_id);
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dev_error(avalon, REASON_DEV_COMMS_ERROR);
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avalon_reset(avalon, fd);
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first_try = 0;
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return 0; /* This should never happen */
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}
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if (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == end_count)) {
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first_try = 1;
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avalon_rotate_array(avalon);
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return 0xffffffff;
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}
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works[i]->blk.nonce = 0xffffffff;
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if (ret == AVA_SEND_BUFFER_FULL)
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break;
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i++;
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}
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if (unlikely(first_try))
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first_try = 0;
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elapsed.tv_sec = elapsed.tv_usec = 0;
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cgtime(&tv_start);
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while (true) {
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full = avalon_buffer_full(fd);
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applog(LOG_DEBUG, "Avalon: Buffer full: %s",
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((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
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if (unlikely(full == AVA_BUFFER_EMPTY))
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break;
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nmsleep(40);
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}
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/* Wait until avalon_send_tasks signals us that it has completed
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* sending its work or a full nonce range timeout has occurred */
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mutex_lock(&info->qlock);
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pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
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mutex_unlock(&info->qlock);
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mutex_lock(&info->lock);
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hash_count = 0xffffffffull * (uint64_t)info->nonces;
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info->nonces = 0;
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mutex_unlock(&info->lock);
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avalon_rotate_array(avalon);
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/* This hashmeter is just a utility counter based on returned shares */
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return hash_count;
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}
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@ -102,7 +102,10 @@ struct avalon_info {
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struct thr_info *thr;
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pthread_t read_thr;
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pthread_t write_thr;
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pthread_mutex_t lock;
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pthread_mutex_t qlock;
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pthread_cond_t qcond;
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int nonces;
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};
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