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1018 lines
25 KiB
1018 lines
25 KiB
/* |
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* Copyright 2013 Con Kolivas <kernel@kolivas.org> |
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* Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com> |
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* Copyright 2012 Luke Dashjr |
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* Copyright 2012 Andrew Smith |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the Free |
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* Software Foundation; either version 3 of the License, or (at your option) |
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* any later version. See COPYING for more details. |
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*/ |
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|
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#include "config.h" |
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|
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#include <limits.h> |
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#include <pthread.h> |
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#include <stdio.h> |
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#include <sys/time.h> |
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#include <sys/types.h> |
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#include <dirent.h> |
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#include <unistd.h> |
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#ifndef WIN32 |
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#include <sys/select.h> |
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#include <termios.h> |
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#include <sys/stat.h> |
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#include <fcntl.h> |
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#ifndef O_CLOEXEC |
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#define O_CLOEXEC 0 |
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#endif |
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#else |
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#include "compat.h" |
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#include <windows.h> |
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#include <io.h> |
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#endif |
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|
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#include "elist.h" |
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#include "miner.h" |
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#include "fpgautils.h" |
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#include "driver-avalon.h" |
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#include "hexdump.c" |
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#include "util.h" |
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static int option_offset = -1; |
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struct avalon_info **avalon_infos; |
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struct device_drv avalon_drv; |
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static int avalon_init_task(struct avalon_task *at, |
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uint8_t reset, uint8_t ff, uint8_t fan, |
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uint8_t timeout, uint8_t asic_num, |
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uint8_t miner_num, uint8_t nonce_elf, |
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uint8_t gate_miner, int frequency) |
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{ |
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uint8_t *buf; |
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static bool first = true; |
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if (unlikely(!at)) |
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return -1; |
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if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0)) |
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return -1; |
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memset(at, 0, sizeof(struct avalon_task)); |
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|
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if (unlikely(reset)) { |
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at->reset = 1; |
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at->fan_eft = 1; |
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at->timer_eft = 1; |
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first = true; |
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} |
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at->flush_fifo = (ff ? 1 : 0); |
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at->fan_eft = (fan ? 1 : 0); |
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if (unlikely(first && !at->reset)) { |
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at->fan_eft = 1; |
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at->timer_eft = 1; |
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first = false; |
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} |
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at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM); |
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at->timeout_data = timeout; |
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at->asic_num = asic_num; |
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at->miner_num = miner_num; |
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at->nonce_elf = nonce_elf; |
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at->gate_miner_elf = 1; |
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at->asic_pll = 1; |
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if (unlikely(gate_miner)) { |
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at-> gate_miner = 1; |
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at->asic_pll = 0; |
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} |
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buf = (uint8_t *)at; |
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buf[5] = 0x00; |
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buf[8] = 0x74; |
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buf[9] = 0x01; |
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buf[10] = 0x00; |
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buf[11] = 0x00; |
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if (frequency == 256) { |
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buf[6] = 0x03; |
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buf[7] = 0x08; |
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} else if (frequency == 270) { |
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buf[6] = 0x73; |
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buf[7] = 0x08; |
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} else if (frequency == 282) { |
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buf[6] = 0xd3; |
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buf[7] = 0x08; |
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} else if (frequency == 300) { |
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buf[6] = 0x63; |
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buf[7] = 0x09; |
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} |
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return 0; |
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} |
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static inline void avalon_create_task(struct avalon_task *at, |
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struct work *work) |
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{ |
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memcpy(at->midstate, work->midstate, 32); |
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memcpy(at->data, work->data + 64, 12); |
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} |
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static int avalon_send_task(int fd, const struct avalon_task *at, |
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struct cgpu_info *avalon) |
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{ |
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size_t ret; |
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int full; |
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struct timespec p; |
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uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM]; |
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size_t nr_len; |
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struct avalon_info *info; |
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uint64_t delay = 32000000; /* Default 32ms for B19200 */ |
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uint32_t nonce_range; |
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int i; |
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if (at->nonce_elf) |
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nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num; |
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else |
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nr_len = AVALON_WRITE_SIZE; |
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memcpy(buf, at, AVALON_WRITE_SIZE); |
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if (at->nonce_elf) { |
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nonce_range = (uint32_t)0xffffffff / at->asic_num; |
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for (i = 0; i < at->asic_num; i++) { |
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buf[AVALON_WRITE_SIZE + (i * 4) + 3] = |
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(i * nonce_range & 0xff000000) >> 24; |
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buf[AVALON_WRITE_SIZE + (i * 4) + 2] = |
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(i * nonce_range & 0x00ff0000) >> 16; |
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buf[AVALON_WRITE_SIZE + (i * 4) + 1] = |
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(i * nonce_range & 0x0000ff00) >> 8; |
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buf[AVALON_WRITE_SIZE + (i * 4) + 0] = |
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(i * nonce_range & 0x000000ff) >> 0; |
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} |
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} |
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#if defined(__BIG_ENDIAN__) || defined(MIPSEB) |
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uint8_t tt = 0; |
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tt = (buf[0] & 0x0f) << 4; |
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tt |= ((buf[0] & 0x10) ? (1 << 3) : 0); |
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tt |= ((buf[0] & 0x20) ? (1 << 2) : 0); |
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tt |= ((buf[0] & 0x40) ? (1 << 1) : 0); |
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tt |= ((buf[0] & 0x80) ? (1 << 0) : 0); |
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buf[0] = tt; |
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tt = (buf[4] & 0x0f) << 4; |
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tt |= ((buf[4] & 0x10) ? (1 << 3) : 0); |
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tt |= ((buf[4] & 0x20) ? (1 << 2) : 0); |
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tt |= ((buf[4] & 0x40) ? (1 << 1) : 0); |
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tt |= ((buf[4] & 0x80) ? (1 << 0) : 0); |
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buf[4] = tt; |
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#endif |
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if (likely(avalon)) { |
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info = avalon->device_data; |
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delay = nr_len * 10 * 1000000000ULL; |
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delay = delay / info->baud; |
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} |
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|
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if (at->reset) |
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nr_len = 1; |
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if (opt_debug) { |
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applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len); |
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hexdump((uint8_t *)buf, nr_len); |
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} |
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ret = write(fd, buf, nr_len); |
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if (unlikely(ret != nr_len)) |
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return AVA_SEND_ERROR; |
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p.tv_sec = 0; |
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p.tv_nsec = (long)delay + 4000000; |
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nanosleep(&p, NULL); |
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applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec); |
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full = avalon_buffer_full(fd); |
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applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s", |
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((full == AVA_BUFFER_FULL) ? "Yes" : "No")); |
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|
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if (unlikely(full == AVA_BUFFER_FULL)) |
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return AVA_SEND_BUFFER_FULL; |
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return AVA_SEND_BUFFER_EMPTY; |
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} |
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static void avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon, |
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struct avalon_info *info, struct avalon_result *ar, |
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struct work *work) |
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{ |
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uint32_t nonce; |
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info = avalon->device_data; |
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info->matching_work[work->subid]++; |
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nonce = htole32(ar->nonce); |
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applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce); |
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submit_nonce(thr, work, nonce); |
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} |
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static int avalon_write(int fd, char *buf, ssize_t len) |
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{ |
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ssize_t wrote = 0; |
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while (len > 0) { |
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struct timeval timeout; |
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ssize_t ret; |
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fd_set wd; |
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timeout.tv_sec = 0; |
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timeout.tv_usec = 100000; |
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FD_ZERO(&wd); |
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FD_SET((SOCKETTYPE)fd, &wd); |
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ret = select(fd + 1, NULL, &wd, NULL, &timeout); |
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if (unlikely(ret < 1)) { |
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applog(LOG_WARNING, "Select error on avalon_write"); |
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return AVA_SEND_ERROR; |
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} |
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ret = write(fd, buf + wrote, len); |
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if (unlikely(ret < 1)) { |
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applog(LOG_WARNING, "Write error on avalon_write"); |
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return AVA_SEND_ERROR; |
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} |
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wrote += ret; |
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len -= ret; |
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} |
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return 0; |
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} |
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static int avalon_read(int fd, char *buf, ssize_t len) |
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{ |
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ssize_t aread = 0; |
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while (len > 0) { |
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struct timeval timeout; |
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ssize_t ret; |
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fd_set rd; |
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timeout.tv_sec = 0; |
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timeout.tv_usec = 100000; |
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FD_ZERO(&rd); |
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FD_SET((SOCKETTYPE)fd, &rd); |
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ret = select(fd + 1, &rd, NULL, NULL, &timeout); |
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if (unlikely(ret < 1)) { |
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applog(LOG_WARNING, "Select error on avalon_read"); |
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return AVA_GETS_ERROR; |
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} |
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ret = read(fd, buf + aread, len); |
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if (unlikely(ret < 1)) { |
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applog(LOG_WARNING, "Read error on avalon_read"); |
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return AVA_GETS_ERROR; |
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} |
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aread += ret; |
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len -= ret; |
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} |
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return 0; |
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} |
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/* Non blocking clearing of anything in the buffer */ |
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static void avalon_clear_readbuf(int fd) |
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{ |
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ssize_t ret; |
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do { |
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struct timeval timeout; |
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char buf[AVALON_FTDI_READSIZE]; |
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fd_set rd; |
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timeout.tv_sec = timeout.tv_usec = 0; |
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FD_ZERO(&rd); |
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FD_SET((SOCKETTYPE)fd, &rd); |
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ret = select(fd + 1, &rd, NULL, NULL, &timeout); |
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if (ret > 0) |
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ret = read(fd, buf, AVALON_FTDI_READSIZE); |
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} while (ret > 0); |
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} |
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static int avalon_reset(struct cgpu_info *avalon, int fd) |
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{ |
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struct avalon_result ar; |
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char reset = 0xad; |
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uint8_t *buf; |
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int ret, i = 0; |
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struct timespec p; |
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/* There's usually a one byte response after opening */ |
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avalon_clear_readbuf(fd); |
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/* Reset once, then send command to go idle */ |
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ret = avalon_write(fd, &reset, 1); |
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if (unlikely(ret == AVA_SEND_ERROR)) |
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return -1; |
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ret = avalon_read(fd, (char *)&ar, AVALON_READ_SIZE); |
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if (unlikely(ret == AVA_GETS_ERROR)) |
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return -1; |
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nanosleep(&p, NULL); |
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buf = (uint8_t *)&ar; |
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if (buf[0] == 0xAA && buf[1] == 0x55 && |
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buf[2] == 0xAA && buf[3] == 0x55) { |
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for (i = 4; i < 11; i++) |
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if (buf[i] != 0) |
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break; |
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} |
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if (i != 11) { |
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applog(LOG_ERR, "AVA%d: Reset failed! not an Avalon?" |
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" (%d: %02x %02x %02x %02x)", avalon->device_id, |
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i, buf[0], buf[1], buf[2], buf[3]); |
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/* FIXME: return 1; */ |
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} else |
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applog(LOG_WARNING, "AVA%d: Reset succeeded", |
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avalon->device_id); |
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/* What do these sleeps do?? */ |
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p.tv_sec = 0; |
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p.tv_nsec = AVALON_RESET_PITCH; |
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nanosleep(&p, NULL); |
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return 0; |
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} |
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static void get_options(int this_option_offset, int *baud, int *miner_count, |
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int *asic_count, int *timeout, int *frequency) |
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{ |
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char err_buf[BUFSIZ+1]; |
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char buf[BUFSIZ+1]; |
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char *ptr, *comma, *colon, *colon2, *colon3, *colon4; |
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size_t max; |
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int i, tmp; |
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|
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if (opt_avalon_options == NULL) |
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buf[0] = '\0'; |
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else { |
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ptr = opt_avalon_options; |
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for (i = 0; i < this_option_offset; i++) { |
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comma = strchr(ptr, ','); |
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if (comma == NULL) |
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break; |
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ptr = comma + 1; |
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} |
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comma = strchr(ptr, ','); |
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if (comma == NULL) |
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max = strlen(ptr); |
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else |
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max = comma - ptr; |
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if (max > BUFSIZ) |
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max = BUFSIZ; |
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strncpy(buf, ptr, max); |
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buf[max] = '\0'; |
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} |
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*baud = AVALON_IO_SPEED; |
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*miner_count = AVALON_DEFAULT_MINER_NUM - 8; |
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*asic_count = AVALON_DEFAULT_ASIC_NUM; |
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*timeout = AVALON_DEFAULT_TIMEOUT; |
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*frequency = AVALON_DEFAULT_FREQUENCY; |
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|
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if (!(*buf)) |
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return; |
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colon = strchr(buf, ':'); |
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if (colon) |
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*(colon++) = '\0'; |
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|
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tmp = atoi(buf); |
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switch (tmp) { |
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case 115200: |
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*baud = 115200; |
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break; |
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case 57600: |
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*baud = 57600; |
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break; |
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case 38400: |
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*baud = 38400; |
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break; |
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case 19200: |
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*baud = 19200; |
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break; |
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default: |
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sprintf(err_buf, |
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"Invalid avalon-options for baud (%s) " |
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"must be 115200, 57600, 38400 or 19200", buf); |
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quit(1, err_buf); |
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} |
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if (colon && *colon) { |
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colon2 = strchr(colon, ':'); |
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if (colon2) |
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*(colon2++) = '\0'; |
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|
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if (*colon) { |
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tmp = atoi(colon); |
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if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) { |
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*miner_count = tmp; |
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} else { |
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sprintf(err_buf, |
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"Invalid avalon-options for " |
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"miner_count (%s) must be 1 ~ %d", |
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colon, AVALON_DEFAULT_MINER_NUM); |
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quit(1, err_buf); |
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} |
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} |
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if (colon2 && *colon2) { |
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colon3 = strchr(colon2, ':'); |
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if (colon3) |
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*(colon3++) = '\0'; |
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|
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tmp = atoi(colon2); |
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if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM) |
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*asic_count = tmp; |
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else { |
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sprintf(err_buf, |
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"Invalid avalon-options for " |
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"asic_count (%s) must be 1 ~ %d", |
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colon2, AVALON_DEFAULT_ASIC_NUM); |
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quit(1, err_buf); |
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} |
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if (colon3 && *colon3) { |
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colon4 = strchr(colon3, ':'); |
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if (colon4) |
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*(colon4++) = '\0'; |
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|
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tmp = atoi(colon3); |
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if (tmp > 0 && tmp <= 0xff) |
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*timeout = tmp; |
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else { |
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sprintf(err_buf, |
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"Invalid avalon-options for " |
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"timeout (%s) must be 1 ~ %d", |
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colon3, 0xff); |
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quit(1, err_buf); |
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} |
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if (colon4 && *colon4) { |
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tmp = atoi(colon4); |
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switch (tmp) { |
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case 256: |
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case 270: |
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case 282: |
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case 300: |
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*frequency = tmp; |
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break; |
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default: |
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sprintf(err_buf, |
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"Invalid avalon-options for " |
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"frequency must be 256/270/282/300"); |
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quit(1, err_buf); |
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} |
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} |
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} |
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} |
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} |
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} |
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|
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static bool avalon_detect_one(const char *devpath) |
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{ |
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struct avalon_info *info; |
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int fd, ret; |
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int baud, miner_count, asic_count, timeout, frequency = 0; |
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struct cgpu_info *avalon; |
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|
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int this_option_offset = ++option_offset; |
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get_options(this_option_offset, &baud, &miner_count, &asic_count, |
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&timeout, &frequency); |
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|
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applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s " |
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"(baud=%d miner_count=%d asic_count=%d timeout=%d frequency=%d)", |
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devpath, baud, miner_count, asic_count, timeout, frequency); |
|
|
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fd = avalon_open2(devpath, baud, true); |
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if (unlikely(fd == -1)) { |
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applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath); |
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return false; |
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} |
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avalon_clear_readbuf(fd); |
|
|
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/* We have a real Avalon! */ |
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avalon = calloc(1, sizeof(struct cgpu_info)); |
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avalon->drv = &avalon_drv; |
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avalon->device_path = strdup(devpath); |
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avalon->device_fd = fd; |
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avalon->threads = AVALON_MINER_THREADS; |
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add_cgpu(avalon); |
|
|
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avalon_infos = realloc(avalon_infos, |
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sizeof(struct avalon_info *) * |
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(total_devices + 1)); |
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|
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applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d", |
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devpath, avalon->device_id); |
|
|
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avalon_infos[avalon->device_id] = calloc(sizeof(struct avalon_info), 1); |
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if (unlikely(!(avalon_infos[avalon->device_id]))) |
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quit(1, "Failed to calloc avalon_infos"); |
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|
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avalon->device_data = avalon_infos[avalon->device_id]; |
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info = avalon->device_data; |
|
|
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info->baud = baud; |
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info->miner_count = miner_count; |
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info->asic_count = asic_count; |
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info->timeout = timeout; |
|
|
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info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM; |
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info->temp_max = 0; |
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/* This is for check the temp/fan every 3~4s */ |
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info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1; |
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if (info->temp_history_count <= 0) |
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info->temp_history_count = 1; |
|
|
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info->temp_history_index = 0; |
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info->temp_sum = 0; |
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info->temp_old = 0; |
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info->frequency = frequency; |
|
|
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ret = avalon_reset(avalon, fd); |
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if (ret) { |
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; /* FIXME: I think IT IS avalon and wait on reset; |
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* avalon_close(fd); |
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* return false; */ |
|
} |
|
|
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return true; |
|
} |
|
|
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static inline void avalon_detect() |
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{ |
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serial_detect(&avalon_drv, avalon_detect_one); |
|
} |
|
|
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static void avalon_init(struct cgpu_info *avalon) |
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{ |
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applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path); |
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} |
|
|
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static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar) |
|
{ |
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return find_queued_work_bymidstate(avalon, (char *)ar->midstate, 32, |
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(char *)ar->data, 64, 12); |
|
} |
|
|
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static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info, |
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struct avalon_result *ar); |
|
|
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static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr) |
|
{ |
|
applog(LOG_WARNING, "%s%d: No valid work - HW error", |
|
thr->cgpu->drv->name, thr->cgpu->device_id); |
|
|
|
inc_hw_errors(thr); |
|
mutex_lock(&info->lock); |
|
info->no_matching_work++; |
|
mutex_unlock(&info->lock); |
|
} |
|
|
|
static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info, |
|
struct thr_info *thr, char *buf, int *offset) |
|
{ |
|
int i, spare = *offset - AVALON_READ_SIZE; |
|
bool found = false; |
|
|
|
for (i = 0; i <= spare; i++) { |
|
struct avalon_result *ar; |
|
struct work *work; |
|
|
|
ar = (struct avalon_result *)&buf[i]; |
|
work = avalon_valid_result(avalon, ar); |
|
if (work) { |
|
bool gettemp = false; |
|
|
|
found = true; |
|
|
|
mutex_lock(&info->lock); |
|
if (!(++avalon->results % info->miner_count)) { |
|
gettemp = true; |
|
avalon->results = 0; |
|
} |
|
info->nonces++; |
|
mutex_unlock(&info->lock); |
|
|
|
avalon_decode_nonce(thr, avalon, info, ar, work); |
|
if (gettemp) |
|
avalon_update_temps(avalon, info, ar); |
|
break; |
|
} |
|
} |
|
|
|
if (!found) { |
|
spare = *offset - AVALON_READ_SIZE; |
|
/* We are buffering and haven't accumulated one more corrupt |
|
* work result. */ |
|
if (spare < (int)AVALON_READ_SIZE) |
|
return; |
|
avalon_inc_nvw(info, thr); |
|
} else { |
|
spare = AVALON_READ_SIZE + i; |
|
if (i) { |
|
if (i >= (int)AVALON_READ_SIZE) |
|
avalon_inc_nvw(info, thr); |
|
else |
|
applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i); |
|
} |
|
} |
|
|
|
*offset -= spare; |
|
memmove(buf, buf + spare, *offset); |
|
} |
|
|
|
static void *avalon_get_results(void *userdata) |
|
{ |
|
struct cgpu_info *avalon = (struct cgpu_info *)userdata; |
|
struct avalon_info *info = avalon->device_data; |
|
const int rsize = AVALON_FTDI_READSIZE; |
|
char readbuf[AVALON_READBUF_SIZE]; |
|
struct thr_info *thr = info->thr; |
|
int fd = avalon->device_fd; |
|
char threadname[24]; |
|
int offset = 0; |
|
|
|
pthread_detach(pthread_self()); |
|
|
|
snprintf(threadname, 24, "ava_recv/%d", avalon->device_id); |
|
RenameThread(threadname); |
|
|
|
while (42) { |
|
struct timeval timeout; |
|
char buf[rsize]; |
|
ssize_t ret; |
|
fd_set rd; |
|
|
|
if (offset >= (int)AVALON_READ_SIZE) |
|
avalon_parse_results(avalon, info, thr, readbuf, &offset); |
|
|
|
if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) { |
|
/* This should never happen */ |
|
applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer"); |
|
offset = 0; |
|
} |
|
|
|
timeout.tv_sec = 0; |
|
timeout.tv_usec = AVALON_READ_TIMEOUT * 1000; |
|
FD_ZERO(&rd); |
|
FD_SET((SOCKETTYPE)fd, &rd); |
|
ret = select(fd + 1, &rd, NULL, NULL, &timeout); |
|
if (ret < 1) { |
|
if (unlikely(ret < 0)) |
|
applog(LOG_WARNING, "Select error in avalon_get_results"); |
|
continue; |
|
} |
|
ret = read(fd, buf, AVALON_FTDI_READSIZE); |
|
if (unlikely(ret < 1)) { |
|
if (unlikely(ret < 0)) |
|
applog(LOG_WARNING, "Read error in avalon_get_results"); |
|
continue; |
|
} |
|
|
|
if (opt_debug) { |
|
applog(LOG_DEBUG, "Avalon: get:"); |
|
hexdump((uint8_t *)buf, ret); |
|
} |
|
|
|
memcpy(&readbuf[offset], buf, ret); |
|
offset += ret; |
|
} |
|
return NULL; |
|
} |
|
|
|
static void avalon_rotate_array(struct cgpu_info *avalon) |
|
{ |
|
avalon->queued = 0; |
|
if (++avalon->work_array >= AVALON_ARRAY_SIZE) |
|
avalon->work_array = 0; |
|
} |
|
|
|
static void *avalon_send_tasks(void *userdata) |
|
{ |
|
struct cgpu_info *avalon = (struct cgpu_info *)userdata; |
|
struct avalon_info *info = avalon->device_data; |
|
const int avalon_get_work_count = info->miner_count; |
|
int fd = avalon->device_fd; |
|
char threadname[24]; |
|
bool idle = false; |
|
|
|
pthread_detach(pthread_self()); |
|
|
|
snprintf(threadname, 24, "ava_send/%d", avalon->device_id); |
|
RenameThread(threadname); |
|
|
|
while (42) { |
|
int start_count, end_count, i, j, ret; |
|
struct avalon_task at; |
|
int idled = 0; |
|
|
|
while (avalon_buffer_full(fd)) { |
|
nmsleep(40); |
|
} |
|
|
|
mutex_lock(&info->qlock); |
|
start_count = avalon->work_array * avalon_get_work_count; |
|
end_count = start_count + avalon_get_work_count; |
|
for (i = start_count, j = 0; i < end_count; i++, j++) { |
|
if (unlikely(avalon_buffer_full(fd))) { |
|
applog(LOG_WARNING, |
|
"AVA%i: Buffer full before all work queued", |
|
avalon->device_id); |
|
break; |
|
} |
|
|
|
if (likely(j < avalon->queued)) { |
|
idle = false; |
|
avalon_init_task(&at, 0, 0, info->fan_pwm, |
|
info->timeout, info->asic_count, |
|
info->miner_count, 1, 0, info->frequency); |
|
avalon_create_task(&at, avalon->works[i]); |
|
} else { |
|
idled++; |
|
avalon_init_task(&at, 0, 0, info->fan_pwm, |
|
info->timeout, info->asic_count, |
|
info->miner_count, 1, 1, info->frequency); |
|
} |
|
ret = avalon_send_task(fd, &at, avalon); |
|
if (unlikely(ret == AVA_SEND_ERROR)) { |
|
applog(LOG_ERR, "AVA%i: Comms error(buffer)", |
|
avalon->device_id); |
|
dev_error(avalon, REASON_DEV_COMMS_ERROR); |
|
avalon_reset(avalon, fd); |
|
} |
|
} |
|
pthread_cond_signal(&info->qcond); |
|
mutex_unlock(&info->qlock); |
|
|
|
if (unlikely(idled && !idle)) { |
|
idle = true; |
|
applog(LOG_WARNING, "AVA%i: Idled %d miners", |
|
avalon->device_id, idled); |
|
} |
|
avalon_rotate_array(avalon); |
|
} |
|
return NULL; |
|
} |
|
|
|
static bool avalon_prepare(struct thr_info *thr) |
|
{ |
|
struct cgpu_info *avalon = thr->cgpu; |
|
struct avalon_info *info = avalon->device_data; |
|
struct timeval now; |
|
|
|
free(avalon->works); |
|
avalon->works = calloc(info->miner_count * sizeof(struct work *), |
|
AVALON_ARRAY_SIZE); |
|
if (!avalon->works) |
|
quit(1, "Failed to calloc avalon works in avalon_prepare"); |
|
|
|
info->thr = thr; |
|
mutex_init(&info->lock); |
|
mutex_init(&info->qlock); |
|
if (unlikely(pthread_cond_init(&info->qcond, NULL))) |
|
quit(1, "Failed to pthread_cond_init avalon qcond"); |
|
|
|
avalon_clear_readbuf(avalon->device_fd); |
|
|
|
if (pthread_create(&info->write_thr, NULL, avalon_send_tasks, (void *)avalon)) |
|
quit(1, "Failed to create avalon write_thr"); |
|
|
|
if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon)) |
|
quit(1, "Failed to create avalon read_thr"); |
|
|
|
avalon_init(avalon); |
|
|
|
cgtime(&now); |
|
get_datestamp(avalon->init, &now); |
|
return true; |
|
} |
|
|
|
static void avalon_free_work(struct thr_info *thr) |
|
{ |
|
struct cgpu_info *avalon; |
|
struct avalon_info *info; |
|
struct work **works; |
|
int i; |
|
|
|
avalon = thr->cgpu; |
|
avalon->queued = 0; |
|
if (unlikely(!avalon->works)) |
|
return; |
|
works = avalon->works; |
|
info = avalon->device_data; |
|
|
|
for (i = 0; i < info->miner_count * 4; i++) { |
|
if (works[i]) { |
|
work_completed(avalon, works[i]); |
|
works[i] = NULL; |
|
} |
|
} |
|
} |
|
|
|
static void do_avalon_close(struct thr_info *thr) |
|
{ |
|
struct cgpu_info *avalon = thr->cgpu; |
|
struct avalon_info *info = avalon->device_data; |
|
|
|
avalon_free_work(thr); |
|
avalon_reset(avalon, avalon->device_fd); |
|
avalon_close(avalon->device_fd); |
|
avalon->device_fd = -1; |
|
|
|
info->no_matching_work = 0; |
|
} |
|
|
|
static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg) |
|
{ |
|
info->fan0 = ar->fan0 * AVALON_FAN_FACTOR; |
|
info->fan1 = ar->fan1 * AVALON_FAN_FACTOR; |
|
info->fan2 = ar->fan2 * AVALON_FAN_FACTOR; |
|
|
|
info->temp0 = ar->temp0; |
|
info->temp1 = ar->temp1; |
|
info->temp2 = ar->temp2; |
|
if (ar->temp0 & 0x80) { |
|
ar->temp0 &= 0x7f; |
|
info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1); |
|
} |
|
if (ar->temp1 & 0x80) { |
|
ar->temp1 &= 0x7f; |
|
info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1); |
|
} |
|
if (ar->temp2 & 0x80) { |
|
ar->temp2 &= 0x7f; |
|
info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1); |
|
} |
|
|
|
*temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1; |
|
|
|
if (info->temp0 > info->temp_max) |
|
info->temp_max = info->temp0; |
|
if (info->temp1 > info->temp_max) |
|
info->temp_max = info->temp1; |
|
if (info->temp2 > info->temp_max) |
|
info->temp_max = info->temp2; |
|
} |
|
|
|
static inline void adjust_fan(struct avalon_info *info) |
|
{ |
|
int temp_new; |
|
|
|
temp_new = info->temp_sum / info->temp_history_count; |
|
|
|
if (temp_new < 35) { |
|
info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM; |
|
info->temp_old = temp_new; |
|
} else if (temp_new > 55) { |
|
info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM; |
|
info->temp_old = temp_new; |
|
} else if (abs(temp_new - info->temp_old) >= 2) { |
|
info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM + (temp_new - 35) * 6.4; |
|
info->temp_old = temp_new; |
|
} |
|
} |
|
|
|
static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info, |
|
struct avalon_result *ar) |
|
{ |
|
record_temp_fan(info, ar, &(avalon->temp)); |
|
applog(LOG_INFO, |
|
"Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t" |
|
"Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC", |
|
info->fan0, info->fan1, info->fan2, |
|
info->temp0, info->temp1, info->temp2, info->temp_max); |
|
info->temp_history_index++; |
|
info->temp_sum += avalon->temp; |
|
applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d", |
|
info->temp_history_index, info->temp_history_count, info->temp_old); |
|
if (info->temp_history_index == info->temp_history_count) { |
|
adjust_fan(info); |
|
info->temp_history_index = 0; |
|
info->temp_sum = 0; |
|
} |
|
} |
|
|
|
/* We use a replacement algorithm to only remove references to work done from |
|
* the buffer when we need the extra space for new work. */ |
|
static bool avalon_fill(struct cgpu_info *avalon) |
|
{ |
|
int subid, slot, mc = avalon_infos[avalon->device_id]->miner_count; |
|
struct avalon_info *info = avalon->device_data; |
|
struct work *work; |
|
bool ret = true; |
|
|
|
mutex_lock(&info->qlock); |
|
if (avalon->queued >= mc) |
|
goto out_unlock; |
|
work = get_queued(avalon); |
|
if (unlikely(!work)) { |
|
ret = false; |
|
goto out_unlock; |
|
} |
|
subid = avalon->queued++; |
|
work->subid = subid; |
|
slot = avalon->work_array * mc + subid; |
|
if (likely(avalon->works[slot])) |
|
work_completed(avalon, avalon->works[slot]); |
|
avalon->works[slot] = work; |
|
if (avalon->queued < mc) |
|
ret = false; |
|
out_unlock: |
|
mutex_unlock(&info->qlock); |
|
|
|
return ret; |
|
} |
|
|
|
static int64_t avalon_scanhash(struct thr_info *thr) |
|
{ |
|
struct cgpu_info *avalon = thr->cgpu; |
|
struct avalon_info *info = avalon->device_data; |
|
struct timeval now, then, tdiff; |
|
int64_t hash_count, us_timeout; |
|
struct timespec abstime; |
|
|
|
/* Full nonce range */ |
|
us_timeout = 0x100000000ll / info->asic_count / info->frequency; |
|
tdiff.tv_sec = us_timeout / 1000000; |
|
tdiff.tv_usec = us_timeout - (tdiff.tv_sec * 1000000); |
|
cgtime(&now); |
|
timeradd(&now, &tdiff, &then); |
|
abstime.tv_sec = then.tv_sec; |
|
abstime.tv_nsec = then.tv_usec * 1000; |
|
|
|
/* Wait until avalon_send_tasks signals us that it has completed |
|
* sending its work or a full nonce range timeout has occurred */ |
|
mutex_lock(&info->qlock); |
|
pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime); |
|
mutex_unlock(&info->qlock); |
|
|
|
mutex_lock(&info->lock); |
|
hash_count = 0xffffffffull * (uint64_t)info->nonces; |
|
info->nonces = 0; |
|
mutex_unlock(&info->lock); |
|
|
|
/* This hashmeter is just a utility counter based on returned shares */ |
|
return hash_count; |
|
} |
|
|
|
static struct api_data *avalon_api_stats(struct cgpu_info *cgpu) |
|
{ |
|
struct api_data *root = NULL; |
|
struct avalon_info *info = cgpu->device_data; |
|
int i; |
|
|
|
root = api_add_int(root, "baud", &(info->baud), false); |
|
root = api_add_int(root, "miner_count", &(info->miner_count),false); |
|
root = api_add_int(root, "asic_count", &(info->asic_count), false); |
|
root = api_add_int(root, "timeout", &(info->timeout), false); |
|
root = api_add_int(root, "frequency", &(info->frequency), false); |
|
|
|
root = api_add_int(root, "fan1", &(info->fan0), false); |
|
root = api_add_int(root, "fan2", &(info->fan1), false); |
|
root = api_add_int(root, "fan3", &(info->fan2), false); |
|
|
|
root = api_add_int(root, "temp1", &(info->temp0), false); |
|
root = api_add_int(root, "temp2", &(info->temp1), false); |
|
root = api_add_int(root, "temp3", &(info->temp2), false); |
|
root = api_add_int(root, "temp_max", &(info->temp_max), false); |
|
|
|
root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false); |
|
for (i = 0; i < info->miner_count; i++) { |
|
char mcw[24]; |
|
|
|
sprintf(mcw, "match_work_count%d", i + 1); |
|
root = api_add_int(root, mcw, &(info->matching_work[i]), false); |
|
} |
|
|
|
return root; |
|
} |
|
|
|
static void avalon_shutdown(struct thr_info *thr) |
|
{ |
|
do_avalon_close(thr); |
|
} |
|
|
|
struct device_drv avalon_drv = { |
|
.drv_id = DRIVER_AVALON, |
|
.dname = "avalon", |
|
.name = "AVA", |
|
.drv_detect = avalon_detect, |
|
.thread_prepare = avalon_prepare, |
|
.hash_work = hash_queued_work, |
|
.queue_full = avalon_fill, |
|
.scanwork = avalon_scanhash, |
|
.get_api_stats = avalon_api_stats, |
|
.reinit_device = avalon_init, |
|
.thread_shutdown = avalon_shutdown, |
|
};
|
|
|