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322 lines
7.4 KiB
322 lines
7.4 KiB
//========= Copyright Valve Corporation, All rights reserved. ============// |
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// |
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// Purpose: |
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// |
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// $NoKeywords: $ |
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// |
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//=============================================================================// |
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#ifndef P4PERFORMANCECOUNTERS_H |
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#define P4PERFORMANCECOUNTERS_H |
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#pragma once |
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// Pentium 4 support |
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/* |
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http://developer.intel.com/design/Pentium4/documentation.htm |
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IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic Architecture |
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IA-32 Intel Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M |
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IA-32 Intel Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z |
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IA-32 Intel Architecture Software Developer's Manual Volume 3: System Programming Guide |
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From Mikael Pettersson's perfctr: |
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http://user.it.uu.se/~mikpe/linux/perfctr/ |
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* Known quirks: |
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- OVF_PMI+FORCE_OVF counters must have an ireset value of -1. |
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This allows the regular overflow check to also handle FORCE_OVF |
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counters. Not having this restriction would lead to MAJOR |
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complications in the driver's "detect overflow counters" code. |
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There is no loss of functionality since the ireset value doesn't |
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affect the counter's PMI rate for FORCE_OVF counters. |
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- In experiments with FORCE_OVF counters, and regular OVF_PMI |
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counters with small ireset values between -8 and -1, it appears |
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that the faulting instruction is subjected to a new PMI before |
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it can complete, ad infinitum. This occurs even though the driver |
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clears the CCCR (and in testing also the ESCR) and invokes a |
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user-space signal handler before restoring the CCCR and resuming |
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the instruction. |
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*/ |
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#define NCOUNTERS 18 |
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// The 18 counters |
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enum Counters |
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{ |
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MSR_BPU_COUNTER0, |
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MSR_BPU_COUNTER1, |
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MSR_BPU_COUNTER2, |
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MSR_BPU_COUNTER3, |
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MSR_MS_COUNTER0, |
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MSR_MS_COUNTER1, |
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MSR_MS_COUNTER2, |
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MSR_MS_COUNTER3, |
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MSR_FLAME_COUNTER0, |
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MSR_FLAME_COUNTER1, |
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MSR_FLAME_COUNTER2, |
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MSR_FLAME_COUNTER3, |
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MSR_IQ_COUNTER0, |
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MSR_IQ_COUNTER1, |
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MSR_IQ_COUNTER2, |
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MSR_IQ_COUNTER3, |
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MSR_IQ_COUNTER4, |
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MSR_IQ_COUNTER5 |
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}; |
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// register base for counters |
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#define MSR_COUNTER_BASE 0x300 |
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// register base for CCCR register |
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#define MSR_CCCR_BASE 0x360 |
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#pragma pack(push, 1) |
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// access to these bits is through the methods |
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typedef union ESCR |
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{ |
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struct |
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{ |
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uint64 Reserved0_1 : 2; // |
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uint64 USR : 1; // |
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uint64 OS : 1; // |
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uint64 TagEnable : 1; // |
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uint64 TagValue : 4; // |
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uint64 EventMask : 16; // from event select |
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uint64 ESCREventSelect : 6; // 31:25 class of event |
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uint64 Reserved31 : 1; // |
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uint64 Reserved32_63 : 32; // |
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}; |
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uint64 flat; |
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} ESCR; |
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typedef union CCCR |
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{ |
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struct |
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{ |
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uint64 Reserved0_11 : 12;// 0 -11 |
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uint64 Enable : 1; // 12 |
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uint64 CCCRSelect : 3; // 13-15 |
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uint64 Reserved16_17 : 2; // 16 17 |
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uint64 Compare : 1; // 18 |
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uint64 Complement : 1; // 19 |
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uint64 Threshold : 4; // 20-23 |
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uint64 Edge : 1; // 24 |
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uint64 FORCE_OVF : 1; // 25 |
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uint64 OVF_PMI : 1; // 26 |
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uint64 Reserved27_29 : 3; // 27-29 |
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uint64 Cascade : 1; // 30 |
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uint64 OVF : 1; // 31 |
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uint64 Reserved32_63 : 32; // |
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}; |
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uint64 flat; |
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} CCCR; |
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#pragma pack(pop) |
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extern const unsigned short cccr_escr_map[NCOUNTERS][8]; |
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enum P4TagState |
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{ |
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TagDisable, // |
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TagEnable, // |
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}; |
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enum P4ForceOverflow |
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{ |
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ForceOverflowDisable, |
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ForceOverflowEnable, |
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}; |
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enum P4OverflowInterrupt |
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{ |
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OverflowInterruptDisable, |
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OverflowInterruptEnable, |
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}; |
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// Turn off the no return value warning in ReadCounter. |
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#pragma warning( disable : 4035 ) |
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class P4BaseEvent |
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{ |
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int m_counter; |
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protected: |
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void SetCounter(int counter) |
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{ |
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m_counter = counter; |
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cccrPort = MSR_CCCR_BASE + m_counter; |
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counterPort = MSR_COUNTER_BASE + m_counter; |
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escrPort = cccr_escr_map[m_counter][cccr.CCCRSelect]; |
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} |
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public: |
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unsigned short m_eventMask; |
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const tchar *description; |
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PME *pme; |
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ESCR escr; |
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CCCR cccr; |
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int counterPort; |
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int cccrPort; |
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int escrPort; |
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P4BaseEvent() |
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{ |
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pme = PME::Instance(); |
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m_eventMask = 0; |
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description = _T(""); |
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escr.flat = 0; |
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cccr.flat = 0; |
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cccr.Reserved16_17 = 3; // must be set |
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escrPort = 0; |
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m_counter = -1; |
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} |
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void StartCounter() |
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{ |
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cccr.Enable = 1; |
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pme->WriteMSR( cccrPort, cccr.flat ); |
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} |
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void StopCounter() |
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{ |
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cccr.Enable = 0; |
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pme->WriteMSR( cccrPort, cccr.flat ); |
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} |
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void ClearCounter() |
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{ |
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pme->WriteMSR( counterPort, 0ui64 ); // clear |
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} |
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void WriteCounter( int64 value ) |
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{ |
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pme->WriteMSR( counterPort, value ); // clear |
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} |
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int64 ReadCounter() |
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{ |
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#if PME_DEBUG |
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if ( escr.USR == 0 && escr.OS == 0 ) |
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return -1; // no area to collect, use SetCaptureMode |
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if ( escr.EventMask == 0 ) |
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return -2; // no event mask set |
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if ( m_counter == -1 ) |
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return -3; // counter not legal |
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#endif |
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// ReadMSR should work here too, but RDPMC should be faster |
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int64 value = 0; |
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pme->ReadMSR( counterPort, &value ); |
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return value; |
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#if 0 |
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// we need to copy this into a temp for some reason |
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int temp = m_counter; |
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_asm |
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{ |
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mov ecx, temp |
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RDPMC |
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} |
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#endif |
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} |
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void SetCaptureMode( PrivilegeCapture priv ) |
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{ |
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switch ( priv ) |
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{ |
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case OS_Only: |
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{ |
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escr.USR = 0; |
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escr.OS = 1; |
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break; |
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} |
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case USR_Only: |
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{ |
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escr.USR = 1; |
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escr.OS = 0; |
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break; |
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} |
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case OS_and_USR: |
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{ |
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escr.USR = 1; |
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escr.OS = 1; |
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break; |
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} |
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} |
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escr.EventMask = m_eventMask; |
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pme->WriteMSR( escrPort, escr.flat ); |
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} |
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void SetTagging( P4TagState tagEnable, uint8 tagValue ) |
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{ |
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escr.TagEnable = tagEnable; |
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escr.TagValue = tagValue; |
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pme->WriteMSR( escrPort, escr.flat ); |
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} |
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void SetFiltering( CompareState compareEnable, CompareMethod compareMethod, uint8 threshold, EdgeState edgeEnable ) |
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{ |
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cccr.Compare = compareEnable; |
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cccr.Complement = compareMethod; |
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cccr.Threshold = threshold; |
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cccr.Edge = edgeEnable; |
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pme->WriteMSR( cccrPort, cccr.flat ); |
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} |
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void SetOverflowEnables( P4ForceOverflow overflowEnable, P4OverflowInterrupt overflowInterruptEnable ) |
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{ |
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cccr.FORCE_OVF = overflowEnable; |
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cccr.OVF_PMI = overflowInterruptEnable; |
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pme->WriteMSR( cccrPort, cccr.flat ); |
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} |
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void SetOverflow() |
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{ |
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cccr.OVF = 1; |
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pme->WriteMSR( cccrPort, cccr.flat ); |
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} |
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void ClearOverflow() |
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{ |
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cccr.OVF = 0; |
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pme->WriteMSR( cccrPort, cccr.flat ); |
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} |
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bool isOverflow() |
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{ |
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CCCR cccr_temp; |
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pme->ReadMSR( cccrPort, &cccr_temp.flat ); |
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return cccr_temp.OVF; |
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} |
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void SetCascade() |
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{ |
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cccr.Cascade = 1; |
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pme->WriteMSR( cccrPort, cccr.flat ); |
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} |
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void ClearCascade() |
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{ |
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cccr.Cascade = 0; |
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pme->WriteMSR( cccrPort, cccr.flat ); |
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} |
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}; |
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#pragma warning( default : 4035 ) |
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#include "EventMasks.h" |
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#include "EventModes.h" |
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#endif // P4PERFORMANCECOUNTERS_H
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