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697 lines
20 KiB
697 lines
20 KiB
//===== Copyright (c) 1996-2005, Valve Corporation, All rights reserved. ======// |
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// |
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// Purpose: |
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// |
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// $NoKeywords: $ |
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//=============================================================================// |
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#include "pch_tier0.h" |
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#if defined(_WIN32) && !defined(_X360) |
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#define WINDOWS_LEAN_AND_MEAN |
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#include <windows.h> |
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#include "cputopology.h" |
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#elif defined( PLATFORM_OSX ) |
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#include <sys/sysctl.h> |
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#endif |
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#ifndef _PS3 |
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#include "tier0_strtools.h" |
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#endif |
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//#include "tier1/strtools.h" // this is included for the definition of V_isspace() |
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#ifdef PLATFORM_WINDOWS_PC |
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#include <intrin.h> |
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#endif |
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// NOTE: This has to be the last file included! |
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#include "tier0/memdbgon.h" |
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const tchar* GetProcessorVendorId(); |
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static bool cpuid(uint32 function, uint32& out_eax, uint32& out_ebx, uint32& out_ecx, uint32& out_edx) |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return false; |
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#elif defined(GNUC) |
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asm("mov %%ebx, %%esi\n\t" |
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"cpuid\n\t" |
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"xchg %%esi, %%ebx" |
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: "=a" (out_eax), |
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"=S" (out_ebx), |
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"=c" (out_ecx), |
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"=d" (out_edx) |
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: "a" (function) |
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); |
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return true; |
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#elif defined(_WIN64) |
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int pCPUInfo[4]; |
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__cpuid( pCPUInfo, (int)function ); |
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out_eax = pCPUInfo[0]; |
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out_ebx = pCPUInfo[1]; |
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out_ecx = pCPUInfo[2]; |
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out_edx = pCPUInfo[3]; |
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return false; |
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#else |
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bool retval = true; |
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uint32 local_eax, local_ebx, local_ecx, local_edx; |
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_asm pushad; |
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__try |
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{ |
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_asm |
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{ |
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xor edx, edx // Clue the compiler that EDX & others is about to be used. |
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xor ecx, ecx |
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xor ebx, ebx // <Sergiy> Note: if I don't zero these out, cpuid sometimes won't work, I didn't find out why yet |
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mov eax, function // set up CPUID to return processor version and features |
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// 0 = vendor string, 1 = version info, 2 = cache info |
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cpuid // code bytes = 0fh, 0a2h |
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mov local_eax, eax // features returned in eax |
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mov local_ebx, ebx // features returned in ebx |
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mov local_ecx, ecx // features returned in ecx |
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mov local_edx, edx // features returned in edx |
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} |
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} |
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__except(EXCEPTION_EXECUTE_HANDLER) |
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{ |
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retval = false; |
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} |
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out_eax = local_eax; |
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out_ebx = local_ebx; |
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out_ecx = local_ecx; |
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out_edx = local_edx; |
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_asm popad |
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return retval; |
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#endif |
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} |
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static bool CheckMMXTechnology(void) |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return true; |
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#else |
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uint32 eax,ebx,edx,unused; |
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if ( !cpuid(1,eax,ebx,unused,edx) ) |
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return false; |
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return ( edx & 0x800000 ) != 0; |
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#endif |
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} |
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//----------------------------------------------------------------------------- |
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// Purpose: This is a bit of a hack because it appears |
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// Output : Returns true on success, false on failure. |
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//----------------------------------------------------------------------------- |
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static bool IsWin98OrOlder() |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) || defined( POSIX ) |
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return false; |
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#else |
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bool retval = false; |
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OSVERSIONINFOEX osvi; |
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ZeroMemory(&osvi, sizeof(OSVERSIONINFOEX)); |
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osvi.dwOSVersionInfoSize = sizeof(OSVERSIONINFOEX); |
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BOOL bOsVersionInfoEx = GetVersionEx ((OSVERSIONINFO *) &osvi); |
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if( !bOsVersionInfoEx ) |
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{ |
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// If OSVERSIONINFOEX doesn't work, try OSVERSIONINFO. |
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osvi.dwOSVersionInfoSize = sizeof (OSVERSIONINFO); |
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if ( !GetVersionEx ( (OSVERSIONINFO *) &osvi) ) |
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{ |
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Error( _T("IsWin98OrOlder: Unable to get OS version information") ); |
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} |
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} |
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switch (osvi.dwPlatformId) |
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{ |
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case VER_PLATFORM_WIN32_NT: |
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// NT, XP, Win2K, etc. all OK for SSE |
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break; |
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case VER_PLATFORM_WIN32_WINDOWS: |
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// Win95, 98, Me can't do SSE |
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retval = true; |
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break; |
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case VER_PLATFORM_WIN32s: |
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// Can't really run this way I don't think... |
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retval = true; |
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break; |
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default: |
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break; |
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} |
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return retval; |
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#endif |
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} |
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static bool CheckSSETechnology(void) |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return true; |
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#else |
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if ( IsWin98OrOlder() ) |
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{ |
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return false; |
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} |
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uint32 eax,ebx,edx,unused; |
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if ( !cpuid(1,eax,ebx,unused,edx) ) |
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{ |
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return false; |
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} |
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return ( edx & 0x2000000L ) != 0; |
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#endif |
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} |
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static bool CheckSSE2Technology(void) |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return false; |
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#else |
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uint32 eax,ebx,edx,unused; |
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if ( !cpuid(1,eax,ebx,unused,edx) ) |
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return false; |
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return ( edx & 0x04000000 ) != 0; |
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#endif |
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} |
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bool CheckSSE3Technology(void) |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return false; |
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#else |
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uint32 eax,ebx,edx,ecx; |
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if( !cpuid(1,eax,ebx,ecx,edx) ) |
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return false; |
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return ( ecx & 0x00000001 ) != 0; // bit 1 of ECX |
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#endif |
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} |
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bool CheckSSSE3Technology(void) |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return false; |
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#else |
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// SSSE 3 is implemented by both Intel and AMD |
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// detection is done the same way for both vendors |
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uint32 eax,ebx,edx,ecx; |
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if( !cpuid(1,eax,ebx,ecx,edx) ) |
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return false; |
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return ( ecx & ( 1 << 9 ) ) != 0; // bit 9 of ECX |
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#endif |
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} |
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bool CheckSSE41Technology(void) |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return false; |
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#else |
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// SSE 4.1 is implemented by both Intel and AMD |
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// detection is done the same way for both vendors |
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uint32 eax,ebx,edx,ecx; |
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if( !cpuid(1,eax,ebx,ecx,edx) ) |
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return false; |
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return ( ecx & ( 1 << 19 ) ) != 0; // bit 19 of ECX |
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#endif |
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} |
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bool CheckSSE42Technology(void) |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return false; |
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#else |
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// SSE4.2 is an Intel-only feature |
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const char *pchVendor = GetProcessorVendorId(); |
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if ( 0 != V_tier0_stricmp( pchVendor, "GenuineIntel" ) ) |
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return false; |
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uint32 eax,ebx,edx,ecx; |
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if( !cpuid(1,eax,ebx,ecx,edx) ) |
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return false; |
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return ( ecx & ( 1 << 20 ) ) != 0; // bit 20 of ECX |
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#endif |
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} |
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bool CheckSSE4aTechnology( void ) |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return false; |
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#else |
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// SSE 4a is an AMD-only feature |
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const char *pchVendor = GetProcessorVendorId(); |
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if ( 0 != V_tier0_stricmp( pchVendor, "AuthenticAMD" ) ) |
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return false; |
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uint32 eax,ebx,edx,ecx; |
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if( !cpuid( 0x80000001,eax,ebx,ecx,edx) ) |
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return false; |
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return ( ecx & ( 1 << 6 ) ) != 0; // bit 6 of ECX |
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#endif |
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} |
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static bool Check3DNowTechnology(void) |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return false; |
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#else |
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uint32 eax, unused; |
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if ( !cpuid(0x80000000,eax,unused,unused,unused) ) |
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return false; |
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if ( eax > 0x80000000L ) |
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{ |
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if ( !cpuid(0x80000001,unused,unused,unused,eax) ) |
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return false; |
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return ( eax & 1<<31 ) != 0; |
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} |
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return false; |
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#endif |
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} |
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static bool CheckCMOVTechnology() |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return false; |
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#else |
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uint32 eax,ebx,edx,unused; |
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if ( !cpuid(1,eax,ebx,unused,edx) ) |
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return false; |
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return ( edx & (1<<15) ) != 0; |
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#endif |
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} |
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static bool CheckFCMOVTechnology(void) |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return false; |
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#else |
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uint32 eax,ebx,edx,unused; |
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if ( !cpuid(1,eax,ebx,unused,edx) ) |
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return false; |
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return ( edx & (1<<16) ) != 0; |
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#endif |
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} |
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static bool CheckRDTSCTechnology(void) |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return false; |
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#else |
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uint32 eax,ebx,edx,unused; |
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if ( !cpuid(1,eax,ebx,unused,edx) ) |
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return false; |
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return ( edx & 0x10 ) != 0; |
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#endif |
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} |
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// Return the Processor's vendor identification string, or "Generic_x86" if it doesn't exist on this CPU |
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const tchar* GetProcessorVendorId() |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) |
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return "PPC"; |
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#else |
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uint32 unused, VendorIDRegisters[3]; |
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static tchar VendorID[13]; |
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memset( VendorID, 0, sizeof(VendorID) ); |
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if ( !cpuid(0,unused, VendorIDRegisters[0], VendorIDRegisters[2], VendorIDRegisters[1] ) ) |
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{ |
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if ( IsPC() ) |
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{ |
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_tcscpy( VendorID, _T( "Generic_x86" ) ); |
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} |
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else if ( IsX360() ) |
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{ |
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_tcscpy( VendorID, _T( "PowerPC" ) ); |
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} |
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} |
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else |
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{ |
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memcpy( VendorID+0, &(VendorIDRegisters[0]), sizeof( VendorIDRegisters[0] ) ); |
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memcpy( VendorID+4, &(VendorIDRegisters[1]), sizeof( VendorIDRegisters[1] ) ); |
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memcpy( VendorID+8, &(VendorIDRegisters[2]), sizeof( VendorIDRegisters[2] ) ); |
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} |
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return VendorID; |
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#endif |
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} |
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// Returns non-zero if Hyper-Threading Technology is supported on the processors and zero if not. |
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// If it's supported, it does not mean that it's been enabled. So we test another flag to see if it's enabled |
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// See Intel Processor Identification and the CPUID instruction Application Note 485 |
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// http://www.intel.com/Assets/PDF/appnote/241618.pdf |
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static bool HTSupported(void) |
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{ |
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#if ( defined( _X360 ) || defined( _PS3 ) ) |
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// not entirtely sure about the semantic of HT support, it being an intel name |
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// are we asking about HW threads or HT? |
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return true; |
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#else |
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enum { |
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HT_BIT = 0x10000000, // EDX[28] - Bit 28 set indicates Hyper-Threading Technology is supported in hardware. |
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FAMILY_ID = 0x0f00, // EAX[11:8] - Bit 11 thru 8 contains family processor id |
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EXT_FAMILY_ID = 0x0f00000, // EAX[23:20] - Bit 23 thru 20 contains extended family processor id |
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FAMILY_ID_386 = 0x0300, |
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FAMILY_ID_486 = 0x0400, // EAX[8:12] - 486, 487 and overdrive |
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FAMILY_ID_PENTIUM = 0x0500, // Pentium, Pentium OverDrive 60 - 200 |
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FAMILY_ID_PENTIUM_PRO = 0x0600,// P Pro, P II, P III, P M, Celeron M, Core Duo, Core Solo, Core2 Duo, Core2 Extreme, P D, Xeon model F, |
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// also 45-nm : Intel Atom, Core i7, Xeon MP ; see Intel Processor Identification and the CPUID instruction pg 20,21 |
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FAMILY_ID_EXTENDED = 0x0F00 // P IV, Xeon, Celeron D, P D, |
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}; |
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uint32 unused, |
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reg_eax = 0, |
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reg_ebx = 0, |
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reg_edx = 0, |
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vendor_id[3] = {0, 0, 0}; |
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// verify cpuid instruction is supported |
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if( !cpuid(0,unused, vendor_id[0],vendor_id[2],vendor_id[1]) |
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|| !cpuid(1,reg_eax,reg_ebx,unused,reg_edx) ) |
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return false; |
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// <Sergiy> Previously, we detected P4 specifically; now, we detect GenuineIntel with HT enabled in general |
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// if (((reg_eax & FAMILY_ID) == FAMILY_ID_EXTENDED) || (reg_eax & EXT_FAMILY_ID)) |
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// Check to see if this is an Intel Processor with HT or CMT capability , and if HT/CMT is enabled |
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if (vendor_id[0] == 'uneG' && vendor_id[1] == 'Ieni' && vendor_id[2] == 'letn') |
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return (reg_edx & HT_BIT) != 0 && // Genuine Intel Processor with Hyper-Threading Technology implemented |
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((reg_ebx >> 16) & 0xFF) > 1 ; // Hyper-Threading OR Core Multi-Processing has been enabled |
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return false; // This is not a genuine Intel processor. |
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#endif |
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} |
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// See Intel Processor Identification and the CPUID instruction Application Note 485 |
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// http://www.intel.com/Assets/PDF/appnote/241618.pdf |
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int LogicalProcessorsPerCore() |
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{ |
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#if defined( _X360 ) || defined( _PS3 ) || defined( LINUX ) |
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return 2; // |
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#elif defined(_WIN32) |
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uint32 nMaxStandardFnSupported, nVendorId[3]; |
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if( !cpuid( 0, nMaxStandardFnSupported,nVendorId[0],nVendorId[2],nVendorId[1] ) ) |
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{ |
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return 1; |
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} |
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uint32 nFn1_Eax, nFn1_Ebx, nFn1_Ecx, nFn1_Edx; |
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if( !cpuid( 1, nFn1_Eax, nFn1_Ebx, nFn1_Ecx, nFn1_Edx) ) |
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{ |
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return 1; |
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} |
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enum CpuidFnMasks |
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{ |
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HTT = 0x10000000, // Fn0000_0001 EDX[28] |
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LogicalProcessorCount = 0x00FF0000, // Fn0000_0001 EBX[23:16] |
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ApicId = 0xFF000000, // Fn0000_0001 EBX[31:24] |
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NC_Intel = 0xFC000000, // Fn0000_0004 EAX[31:26] |
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NC_Amd = 0x000000FF, // Fn8000_0008 ECX[7:0] |
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CmpLegacy_Amd = 0x00000002, // Fn8000_0001 ECX[1] |
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ApicIdCoreIdSize_Amd = 0x0000F000 // Fn8000_0008 ECX[15:12] |
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}; |
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// Determine if hardware threading is enabled. |
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if( nFn1_Edx & HTT ) |
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{ |
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// Determine the total number of logical processors per package. |
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int nLogProcsPerPkg = ( nFn1_Ebx & LogicalProcessorCount ) >> 16; |
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int nCoresPerPkg = 1; |
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if( ( ( nFn1_Ebx >> 16 ) & 0xFF ) <= 1 ) // Has Hyper-Threading OR Core Multi-Processing not been enabled ? |
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{ |
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// NOTE: This is only tested on Intel CPUs; I don't know if it's true on AMD, as I have no HT AMD to test on |
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return 1; // HT was turned off, for all intents and purposes in our engine it means one logical CPU per core |
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} |
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// Determine the total number of cores per package. This info |
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// is extracted differently dependending on the cpu vendor. |
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if( nVendorId[0] == 'uneG' && nVendorId[1] == 'Ieni' && nVendorId[2] == 'letn' ) // GenuineIntel |
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{ |
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if( nMaxStandardFnSupported >= 4 ) |
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{ |
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uint32 nFn4_Eax, nFn4_Ebx, nFn4_Ecx, nFn4_Edx ; |
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if( cpuid( 4, nFn4_Eax, nFn4_Ebx, nFn4_Ecx, nFn4_Edx ) ) |
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{ |
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nCoresPerPkg = ( ( nFn4_Eax & NC_Intel ) >> 26 ) + 1; |
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} |
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} |
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// <Sergiy> as the DirectX CoreDetection sample goes, the logic is that on old processors where |
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// the functions aren't supported, we assume one core per package, multiple logical processors per package |
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// I suspect this may be wrong, especially for AMD processors. |
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return nLogProcsPerPkg / nCoresPerPkg; |
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} |
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#if 0 // <Sergiy> To make as concervative change as possible now, I'll skip AMD hyperthread detection |
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else |
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{ |
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if( nVendorId[0] == 'htuA' && nVendorId[1] == 'itne' && nVendorId[2] == 'DMAc' ) // AuthenticAMD |
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{ |
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uint32 nFnx8_Eax, nFnx8_Ebx, nFnx8_Ecx, nFnx8_Edx ; |
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if( cpuid( 0x80000008, nFnx8_Eax, nFnx8_Ebx, nFnx8_Ecx, nFnx8_Edx ) ) |
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{ |
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// AMD reports the msb width of the CORE_ID bit field of the APIC ID |
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// in ApicIdCoreIdSize_Amd. The maximum value represented by the msb |
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// width is the theoretical number of cores the processor can support |
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// and not the actual number of current cores, which is how the msb width |
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// of the CORE_ID bit field has been traditionally determined. If the |
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// ApicIdCoreIdSize_Amd value is zero, then you use the traditional method |
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// to determine the CORE_ID msb width. |
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DWORD msbWidth = nFnx8_Ecx & ApicIdCoreIdSize_Amd; |
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if( msbWidth ) |
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{ |
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// Set nCoresPerPkg to the maximum theortical number of cores |
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// the processor package can support (2 ^ width) so the APIC |
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// extractor object can be configured to extract the proper |
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// values from an APIC. |
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nCoresPerPkg = 1 << ( msbWidth >> 12 ); |
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} |
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else |
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{ |
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// Set nCoresPerPkg to the actual number of cores being reported |
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// by the CPUID instruction. |
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nCoresPerPkg = ( nFnx8_Ecx & NC_Amd ) + 1; |
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} |
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} |
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} |
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// <Sergiy> as the DirectX CoreDetection sample goes, the logic is that on old processors where |
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// the functions aren't supported, we assume one core per package, multiple logical processors per package |
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// I suspect this may be wrong, especially for AMD processors. |
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return nLogProcsPerPkg / nCoresPerPkg; |
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} |
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#endif |
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} |
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return 1; |
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#endif |
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} |
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// Measure the processor clock speed by sampling the cycle count, waiting |
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// for some fraction of a second, then measuring the elapsed number of cycles. |
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static int64 CalculateClockSpeed() |
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{ |
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#if defined( _X360 ) || defined(_PS3) |
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// Xbox360 and PS3 have the same clock speed and share a lot of characteristics on PPU |
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return 3200000000LL; |
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#else |
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#if defined( _WIN32 ) |
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LARGE_INTEGER waitTime, startCount, curCount; |
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CCycleCount start, end; |
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// Take 1/32 of a second for the measurement. |
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QueryPerformanceFrequency( &waitTime ); |
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int scale = 5; |
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waitTime.QuadPart >>= scale; |
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QueryPerformanceCounter( &startCount ); |
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start.Sample(); |
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do |
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{ |
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QueryPerformanceCounter( &curCount ); |
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} |
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while ( curCount.QuadPart - startCount.QuadPart < waitTime.QuadPart ); |
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end.Sample(); |
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return (end.m_Int64 - start.m_Int64) << scale; |
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#elif defined(POSIX) |
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uint64 CalculateCPUFreq(); // from cpu_linux.cpp |
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int64 freq =(int64)CalculateCPUFreq(); |
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if ( freq == 0 ) // couldn't calculate clock speed |
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{ |
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Error( "Unable to determine CPU Frequency\n" ); |
|
} |
|
return freq; |
|
#else |
|
#error "Please implement Clock Speed function for this platform" |
|
#endif |
|
#endif |
|
} |
|
|
|
static CPUInformation s_cpuInformation; |
|
|
|
const CPUInformation& GetCPUInformation() |
|
{ |
|
CPUInformation &pi = s_cpuInformation; |
|
// Has the structure already been initialized and filled out? |
|
if ( pi.m_Size == sizeof(pi) ) |
|
return pi; |
|
|
|
// Redundant, but just in case the user somehow messes with the size. |
|
memset(&pi, 0x0, sizeof(pi)); |
|
|
|
// Fill out the structure, and return it: |
|
pi.m_Size = sizeof(pi); |
|
|
|
// Grab the processor frequency: |
|
pi.m_Speed = CalculateClockSpeed(); |
|
|
|
// Get the logical and physical processor counts: |
|
|
|
#if defined( _X360 ) |
|
pi.m_nPhysicalProcessors = 3; |
|
pi.m_nLogicalProcessors = 6; |
|
#elif defined( _PS3 ) |
|
pi.m_nPhysicalProcessors = 1; |
|
pi.m_nLogicalProcessors = 2; |
|
#elif defined(_WIN32) && !defined( _X360 ) |
|
SYSTEM_INFO si; |
|
ZeroMemory( &si, sizeof(si) ); |
|
|
|
GetSystemInfo( &si ); |
|
|
|
// Sergiy: fixing: si.dwNumberOfProcessors is the number of logical processors according to experiments on i7, P4 and a DirectX sample (Aug'09) |
|
// this is contrary to MSDN documentation on GetSystemInfo() |
|
// |
|
pi.m_nLogicalProcessors = si.dwNumberOfProcessors; |
|
if ( 0 == V_tier0_stricmp( GetProcessorVendorId(), "AuthenticAMD" ) ) |
|
{ |
|
// quick fix for AMD Phenom: it reports 3 logical cores and 4 physical cores; |
|
// no AMD CPUs by the end of 2009 have HT, so we'll override HT detection here |
|
pi.m_nPhysicalProcessors = pi.m_nLogicalProcessors; |
|
} |
|
else |
|
{ |
|
CpuTopology topo; |
|
pi.m_nPhysicalProcessors = topo.NumberOfSystemCores(); |
|
} |
|
|
|
// Make sure I always report at least one, when running WinXP with the /ONECPU switch, |
|
// it likes to report 0 processors for some reason. |
|
if ( pi.m_nPhysicalProcessors == 0 && pi.m_nLogicalProcessors == 0 ) |
|
{ |
|
Assert( !"Sergiy: apparently I didn't fix some CPU detection code completely. Let me know and I'll do my best to fix it soon." ); |
|
pi.m_nPhysicalProcessors = 1; |
|
pi.m_nLogicalProcessors = 1; |
|
} |
|
#elif defined(LINUX) |
|
pi.m_nLogicalProcessors = 0; |
|
pi.m_nPhysicalProcessors = 0; |
|
const int k_cMaxProcessors = 256; |
|
bool rgbProcessors[k_cMaxProcessors]; |
|
memset( rgbProcessors, 0, sizeof( rgbProcessors ) ); |
|
int cMaxCoreId = 0; |
|
|
|
FILE *fpCpuInfo = fopen( "/proc/cpuinfo", "r" ); |
|
if ( fpCpuInfo ) |
|
{ |
|
char rgchLine[256]; |
|
while ( fgets( rgchLine, sizeof( rgchLine ), fpCpuInfo ) ) |
|
{ |
|
if ( !strncasecmp( rgchLine, "processor", strlen( "processor" ) ) ) |
|
{ |
|
pi.m_nLogicalProcessors++; |
|
} |
|
if ( !strncasecmp( rgchLine, "core id", strlen( "core id" ) ) ) |
|
{ |
|
char *pchValue = strchr( rgchLine, ':' ); |
|
cMaxCoreId = MAX( cMaxCoreId, atoi( pchValue + 1 ) ); |
|
} |
|
if ( !strncasecmp( rgchLine, "physical id", strlen( "physical id" ) ) ) |
|
{ |
|
// it seems (based on survey data) that we can see |
|
// processor N (N > 0) when it's the only processor in |
|
// the system. so keep track of each processor |
|
char *pchValue = strchr( rgchLine, ':' ); |
|
int cPhysicalId = atoi( pchValue + 1 ); |
|
if ( cPhysicalId < k_cMaxProcessors ) |
|
rgbProcessors[cPhysicalId] = true; |
|
} |
|
/* this code will tell us how many physical chips are in the machine, but we want |
|
core count, so for the moment, each processor counts as both logical and physical. |
|
if ( !strncasecmp( rgchLine, "physical id ", strlen( "physical id " ) ) ) |
|
{ |
|
char *pchValue = strchr( rgchLine, ':' ); |
|
pi.m_nPhysicalProcessors = MAX( pi.m_nPhysicalProcessors, atol( pchValue ) ); |
|
} |
|
*/ |
|
} |
|
fclose( fpCpuInfo ); |
|
for ( int i = 0; i < k_cMaxProcessors; i++ ) |
|
if ( rgbProcessors[i] ) |
|
pi.m_nPhysicalProcessors++; |
|
pi.m_nPhysicalProcessors *= ( cMaxCoreId + 1 ); |
|
} |
|
else |
|
{ |
|
pi.m_nLogicalProcessors = 1; |
|
pi.m_nPhysicalProcessors = 1; |
|
Assert( !"couldn't read cpu information from /proc/cpuinfo" ); |
|
} |
|
|
|
#elif defined(OSX) |
|
int mib[2], num_cpu = 1; |
|
size_t len; |
|
mib[0] = CTL_HW; |
|
mib[1] = HW_NCPU; |
|
len = sizeof(num_cpu); |
|
sysctl(mib, 2, &num_cpu, &len, NULL, 0); |
|
pi.m_nPhysicalProcessors = num_cpu; |
|
pi.m_nLogicalProcessors = num_cpu; |
|
|
|
#endif |
|
|
|
// Determine Processor Features: |
|
pi.m_bRDTSC = CheckRDTSCTechnology(); |
|
pi.m_bCMOV = CheckCMOVTechnology(); |
|
pi.m_bFCMOV = CheckFCMOVTechnology(); |
|
pi.m_bMMX = CheckMMXTechnology(); |
|
pi.m_bSSE = CheckSSETechnology(); |
|
pi.m_bSSE2 = CheckSSE2Technology(); |
|
pi.m_bSSE3 = CheckSSE3Technology(); |
|
pi.m_bSSSE3 = CheckSSSE3Technology(); |
|
pi.m_bSSE4a = CheckSSE4aTechnology(); |
|
pi.m_bSSE41 = CheckSSE41Technology(); |
|
pi.m_bSSE42 = CheckSSE42Technology(); |
|
pi.m_b3DNow = Check3DNowTechnology(); |
|
pi.m_szProcessorID = (tchar*)GetProcessorVendorId(); |
|
pi.m_bHT = pi.m_nPhysicalProcessors < pi.m_nLogicalProcessors; //HTSupported(); |
|
|
|
return pi; |
|
} |
|
|
|
|