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429 lines
11 KiB
429 lines
11 KiB
#!/usr/bin/env perl |
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# |
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# ==================================================================== |
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# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL |
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# project. The module is, however, dual licensed under OpenSSL and |
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# CRYPTOGAMS licenses depending on where you obtain it. For further |
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# details see http://www.openssl.org/~appro/cryptogams/. |
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# ==================================================================== |
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# |
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# April 2010 |
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# |
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# The module implements "4-bit" GCM GHASH function and underlying |
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# single multiplication operation in GF(2^128). "4-bit" means that it |
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# uses 256 bytes per-key table [+32 bytes shared table]. There is no |
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# experimental performance data available yet. The only approximation |
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# that can be made at this point is based on code size. Inner loop is |
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# 32 instructions long and on single-issue core should execute in <40 |
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# cycles. Having verified that gcc 3.4 didn't unroll corresponding |
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# loop, this assembler loop body was found to be ~3x smaller than |
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# compiler-generated one... |
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# |
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# July 2010 |
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# |
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# Rescheduling for dual-issue pipeline resulted in 8.5% improvement on |
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# Cortex A8 core and ~25 cycles per processed byte (which was observed |
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# to be ~3 times faster than gcc-generated code:-) |
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# |
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# February 2011 |
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# |
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# Profiler-assisted and platform-specific optimization resulted in 7% |
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# improvement on Cortex A8 core and ~23.5 cycles per byte. |
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# |
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# March 2011 |
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# |
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# Add NEON implementation featuring polynomial multiplication, i.e. no |
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# lookup tables involved. On Cortex A8 it was measured to process one |
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# byte in 15 cycles or 55% faster than integer-only code. |
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# ==================================================================== |
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# Note about "528B" variant. In ARM case it makes lesser sense to |
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# implement it for following reasons: |
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# |
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# - performance improvement won't be anywhere near 50%, because 128- |
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# bit shift operation is neatly fused with 128-bit xor here, and |
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# "538B" variant would eliminate only 4-5 instructions out of 32 |
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# in the inner loop (meaning that estimated improvement is ~15%); |
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# - ARM-based systems are often embedded ones and extra memory |
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# consumption might be unappreciated (for so little improvement); |
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# |
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# Byte order [in]dependence. ========================================= |
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# |
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# Caller is expected to maintain specific *dword* order in Htable, |
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# namely with *least* significant dword of 128-bit value at *lower* |
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# address. This differs completely from C code and has everything to |
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# do with ldm instruction and order in which dwords are "consumed" by |
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# algorithm. *Byte* order within these dwords in turn is whatever |
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# *native* byte order on current platform. See gcm128.c for working |
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# example... |
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while (($output=shift) && ($output!~/^\w[\w\-]*\.\w+$/)) {} |
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open STDOUT,">$output"; |
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$Xi="r0"; # argument block |
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$Htbl="r1"; |
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$inp="r2"; |
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$len="r3"; |
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$Zll="r4"; # variables |
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$Zlh="r5"; |
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$Zhl="r6"; |
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$Zhh="r7"; |
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$Tll="r8"; |
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$Tlh="r9"; |
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$Thl="r10"; |
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$Thh="r11"; |
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$nlo="r12"; |
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################# r13 is stack pointer |
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$nhi="r14"; |
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################# r15 is program counter |
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$rem_4bit=$inp; # used in gcm_gmult_4bit |
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$cnt=$len; |
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sub Zsmash() { |
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my $i=12; |
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my @args=@_; |
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for ($Zll,$Zlh,$Zhl,$Zhh) { |
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$code.=<<___; |
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#if __ARM_ARCH__>=7 && defined(__ARMEL__) |
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rev $_,$_ |
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str $_,[$Xi,#$i] |
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#elif defined(__ARMEB__) |
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str $_,[$Xi,#$i] |
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#else |
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mov $Tlh,$_,lsr#8 |
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strb $_,[$Xi,#$i+3] |
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mov $Thl,$_,lsr#16 |
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strb $Tlh,[$Xi,#$i+2] |
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mov $Thh,$_,lsr#24 |
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strb $Thl,[$Xi,#$i+1] |
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strb $Thh,[$Xi,#$i] |
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#endif |
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___ |
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$code.="\t".shift(@args)."\n"; |
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$i-=4; |
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} |
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} |
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$code=<<___; |
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#include "arm_arch.h" |
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.text |
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.code 32 |
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.type rem_4bit,%object |
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.align 5 |
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rem_4bit: |
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.short 0x0000,0x1C20,0x3840,0x2460 |
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.short 0x7080,0x6CA0,0x48C0,0x54E0 |
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.short 0xE100,0xFD20,0xD940,0xC560 |
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.short 0x9180,0x8DA0,0xA9C0,0xB5E0 |
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.size rem_4bit,.-rem_4bit |
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.type rem_4bit_get,%function |
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rem_4bit_get: |
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sub $rem_4bit,pc,#8 |
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sub $rem_4bit,$rem_4bit,#32 @ &rem_4bit |
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b .Lrem_4bit_got |
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nop |
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.size rem_4bit_get,.-rem_4bit_get |
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.global gcm_ghash_4bit |
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.type gcm_ghash_4bit,%function |
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gcm_ghash_4bit: |
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sub r12,pc,#8 |
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add $len,$inp,$len @ $len to point at the end |
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stmdb sp!,{r3-r11,lr} @ save $len/end too |
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sub r12,r12,#48 @ &rem_4bit |
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ldmia r12,{r4-r11} @ copy rem_4bit ... |
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stmdb sp!,{r4-r11} @ ... to stack |
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ldrb $nlo,[$inp,#15] |
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ldrb $nhi,[$Xi,#15] |
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.Louter: |
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eor $nlo,$nlo,$nhi |
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and $nhi,$nlo,#0xf0 |
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and $nlo,$nlo,#0x0f |
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mov $cnt,#14 |
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add $Zhh,$Htbl,$nlo,lsl#4 |
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ldmia $Zhh,{$Zll-$Zhh} @ load Htbl[nlo] |
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add $Thh,$Htbl,$nhi |
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ldrb $nlo,[$inp,#14] |
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and $nhi,$Zll,#0xf @ rem |
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ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi] |
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add $nhi,$nhi,$nhi |
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eor $Zll,$Tll,$Zll,lsr#4 |
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ldrh $Tll,[sp,$nhi] @ rem_4bit[rem] |
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eor $Zll,$Zll,$Zlh,lsl#28 |
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ldrb $nhi,[$Xi,#14] |
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eor $Zlh,$Tlh,$Zlh,lsr#4 |
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eor $Zlh,$Zlh,$Zhl,lsl#28 |
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eor $Zhl,$Thl,$Zhl,lsr#4 |
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eor $Zhl,$Zhl,$Zhh,lsl#28 |
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eor $Zhh,$Thh,$Zhh,lsr#4 |
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eor $nlo,$nlo,$nhi |
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and $nhi,$nlo,#0xf0 |
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and $nlo,$nlo,#0x0f |
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eor $Zhh,$Zhh,$Tll,lsl#16 |
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.Linner: |
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add $Thh,$Htbl,$nlo,lsl#4 |
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and $nlo,$Zll,#0xf @ rem |
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subs $cnt,$cnt,#1 |
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add $nlo,$nlo,$nlo |
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ldmia $Thh,{$Tll-$Thh} @ load Htbl[nlo] |
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eor $Zll,$Tll,$Zll,lsr#4 |
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eor $Zll,$Zll,$Zlh,lsl#28 |
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eor $Zlh,$Tlh,$Zlh,lsr#4 |
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eor $Zlh,$Zlh,$Zhl,lsl#28 |
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ldrh $Tll,[sp,$nlo] @ rem_4bit[rem] |
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eor $Zhl,$Thl,$Zhl,lsr#4 |
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ldrplb $nlo,[$inp,$cnt] |
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eor $Zhl,$Zhl,$Zhh,lsl#28 |
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eor $Zhh,$Thh,$Zhh,lsr#4 |
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add $Thh,$Htbl,$nhi |
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and $nhi,$Zll,#0xf @ rem |
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eor $Zhh,$Zhh,$Tll,lsl#16 @ ^= rem_4bit[rem] |
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add $nhi,$nhi,$nhi |
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ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi] |
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eor $Zll,$Tll,$Zll,lsr#4 |
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ldrplb $Tll,[$Xi,$cnt] |
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eor $Zll,$Zll,$Zlh,lsl#28 |
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eor $Zlh,$Tlh,$Zlh,lsr#4 |
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ldrh $Tlh,[sp,$nhi] |
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eor $Zlh,$Zlh,$Zhl,lsl#28 |
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eor $Zhl,$Thl,$Zhl,lsr#4 |
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eor $Zhl,$Zhl,$Zhh,lsl#28 |
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eorpl $nlo,$nlo,$Tll |
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eor $Zhh,$Thh,$Zhh,lsr#4 |
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andpl $nhi,$nlo,#0xf0 |
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andpl $nlo,$nlo,#0x0f |
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eor $Zhh,$Zhh,$Tlh,lsl#16 @ ^= rem_4bit[rem] |
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bpl .Linner |
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ldr $len,[sp,#32] @ re-load $len/end |
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add $inp,$inp,#16 |
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mov $nhi,$Zll |
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___ |
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&Zsmash("cmp\t$inp,$len","ldrneb\t$nlo,[$inp,#15]"); |
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$code.=<<___; |
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bne .Louter |
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add sp,sp,#36 |
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#if __ARM_ARCH__>=5 |
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ldmia sp!,{r4-r11,pc} |
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#else |
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ldmia sp!,{r4-r11,lr} |
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tst lr,#1 |
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moveq pc,lr @ be binary compatible with V4, yet |
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bx lr @ interoperable with Thumb ISA:-) |
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#endif |
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.size gcm_ghash_4bit,.-gcm_ghash_4bit |
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.global gcm_gmult_4bit |
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.type gcm_gmult_4bit,%function |
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gcm_gmult_4bit: |
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stmdb sp!,{r4-r11,lr} |
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ldrb $nlo,[$Xi,#15] |
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b rem_4bit_get |
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.Lrem_4bit_got: |
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and $nhi,$nlo,#0xf0 |
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and $nlo,$nlo,#0x0f |
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mov $cnt,#14 |
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add $Zhh,$Htbl,$nlo,lsl#4 |
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ldmia $Zhh,{$Zll-$Zhh} @ load Htbl[nlo] |
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ldrb $nlo,[$Xi,#14] |
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add $Thh,$Htbl,$nhi |
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and $nhi,$Zll,#0xf @ rem |
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ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi] |
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add $nhi,$nhi,$nhi |
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eor $Zll,$Tll,$Zll,lsr#4 |
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ldrh $Tll,[$rem_4bit,$nhi] @ rem_4bit[rem] |
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eor $Zll,$Zll,$Zlh,lsl#28 |
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eor $Zlh,$Tlh,$Zlh,lsr#4 |
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eor $Zlh,$Zlh,$Zhl,lsl#28 |
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eor $Zhl,$Thl,$Zhl,lsr#4 |
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eor $Zhl,$Zhl,$Zhh,lsl#28 |
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eor $Zhh,$Thh,$Zhh,lsr#4 |
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and $nhi,$nlo,#0xf0 |
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eor $Zhh,$Zhh,$Tll,lsl#16 |
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and $nlo,$nlo,#0x0f |
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.Loop: |
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add $Thh,$Htbl,$nlo,lsl#4 |
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and $nlo,$Zll,#0xf @ rem |
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subs $cnt,$cnt,#1 |
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add $nlo,$nlo,$nlo |
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ldmia $Thh,{$Tll-$Thh} @ load Htbl[nlo] |
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eor $Zll,$Tll,$Zll,lsr#4 |
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eor $Zll,$Zll,$Zlh,lsl#28 |
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eor $Zlh,$Tlh,$Zlh,lsr#4 |
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eor $Zlh,$Zlh,$Zhl,lsl#28 |
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ldrh $Tll,[$rem_4bit,$nlo] @ rem_4bit[rem] |
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eor $Zhl,$Thl,$Zhl,lsr#4 |
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ldrplb $nlo,[$Xi,$cnt] |
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eor $Zhl,$Zhl,$Zhh,lsl#28 |
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eor $Zhh,$Thh,$Zhh,lsr#4 |
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add $Thh,$Htbl,$nhi |
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and $nhi,$Zll,#0xf @ rem |
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eor $Zhh,$Zhh,$Tll,lsl#16 @ ^= rem_4bit[rem] |
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add $nhi,$nhi,$nhi |
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ldmia $Thh,{$Tll-$Thh} @ load Htbl[nhi] |
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eor $Zll,$Tll,$Zll,lsr#4 |
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eor $Zll,$Zll,$Zlh,lsl#28 |
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eor $Zlh,$Tlh,$Zlh,lsr#4 |
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ldrh $Tll,[$rem_4bit,$nhi] @ rem_4bit[rem] |
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eor $Zlh,$Zlh,$Zhl,lsl#28 |
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eor $Zhl,$Thl,$Zhl,lsr#4 |
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eor $Zhl,$Zhl,$Zhh,lsl#28 |
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eor $Zhh,$Thh,$Zhh,lsr#4 |
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andpl $nhi,$nlo,#0xf0 |
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andpl $nlo,$nlo,#0x0f |
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eor $Zhh,$Zhh,$Tll,lsl#16 @ ^= rem_4bit[rem] |
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bpl .Loop |
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___ |
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&Zsmash(); |
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$code.=<<___; |
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#if __ARM_ARCH__>=5 |
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ldmia sp!,{r4-r11,pc} |
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#else |
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ldmia sp!,{r4-r11,lr} |
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tst lr,#1 |
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moveq pc,lr @ be binary compatible with V4, yet |
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bx lr @ interoperable with Thumb ISA:-) |
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#endif |
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.size gcm_gmult_4bit,.-gcm_gmult_4bit |
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___ |
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{ |
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my $cnt=$Htbl; # $Htbl is used once in the very beginning |
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my ($Hhi, $Hlo, $Zo, $T, $xi, $mod) = map("d$_",(0..7)); |
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my ($Qhi, $Qlo, $Z, $R, $zero, $Qpost, $IN) = map("q$_",(8..15)); |
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# Z:Zo keeps 128-bit result shifted by 1 to the right, with bottom bit |
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# in Zo. Or should I say "top bit", because GHASH is specified in |
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# reverse bit order? Otherwise straightforward 128-bt H by one input |
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# byte multiplication and modulo-reduction, times 16. |
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sub Dlo() { shift=~m|q([1]?[0-9])|?"d".($1*2):""; } |
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sub Dhi() { shift=~m|q([1]?[0-9])|?"d".($1*2+1):""; } |
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sub Q() { shift=~m|d([1-3]?[02468])|?"q".($1/2):""; } |
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$code.=<<___; |
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#if __ARM_ARCH__>=7 |
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.fpu neon |
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.global gcm_gmult_neon |
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.type gcm_gmult_neon,%function |
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.align 4 |
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gcm_gmult_neon: |
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sub $Htbl,#16 @ point at H in GCM128_CTX |
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vld1.64 `&Dhi("$IN")`,[$Xi,:64]!@ load Xi |
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vmov.i32 $mod,#0xe1 @ our irreducible polynomial |
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vld1.64 `&Dlo("$IN")`,[$Xi,:64]! |
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vshr.u64 $mod,#32 |
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vldmia $Htbl,{$Hhi-$Hlo} @ load H |
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veor $zero,$zero |
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#ifdef __ARMEL__ |
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vrev64.8 $IN,$IN |
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#endif |
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veor $Qpost,$Qpost |
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veor $R,$R |
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mov $cnt,#16 |
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veor $Z,$Z |
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mov $len,#16 |
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veor $Zo,$Zo |
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vdup.8 $xi,`&Dlo("$IN")`[0] @ broadcast lowest byte |
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b .Linner_neon |
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.size gcm_gmult_neon,.-gcm_gmult_neon |
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.global gcm_ghash_neon |
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.type gcm_ghash_neon,%function |
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.align 4 |
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gcm_ghash_neon: |
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vld1.64 `&Dhi("$Z")`,[$Xi,:64]! @ load Xi |
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vmov.i32 $mod,#0xe1 @ our irreducible polynomial |
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vld1.64 `&Dlo("$Z")`,[$Xi,:64]! |
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vshr.u64 $mod,#32 |
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vldmia $Xi,{$Hhi-$Hlo} @ load H |
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veor $zero,$zero |
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nop |
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#ifdef __ARMEL__ |
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vrev64.8 $Z,$Z |
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#endif |
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.Louter_neon: |
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vld1.64 `&Dhi($IN)`,[$inp]! @ load inp |
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veor $Qpost,$Qpost |
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vld1.64 `&Dlo($IN)`,[$inp]! |
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veor $R,$R |
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mov $cnt,#16 |
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#ifdef __ARMEL__ |
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vrev64.8 $IN,$IN |
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#endif |
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veor $Zo,$Zo |
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veor $IN,$Z @ inp^=Xi |
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veor $Z,$Z |
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vdup.8 $xi,`&Dlo("$IN")`[0] @ broadcast lowest byte |
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.Linner_neon: |
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subs $cnt,$cnt,#1 |
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vmull.p8 $Qlo,$Hlo,$xi @ H.lo·Xi[i] |
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vmull.p8 $Qhi,$Hhi,$xi @ H.hi·Xi[i] |
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vext.8 $IN,$zero,#1 @ IN>>=8 |
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veor $Z,$Qpost @ modulo-scheduled part |
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vshl.i64 `&Dlo("$R")`,#48 |
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vdup.8 $xi,`&Dlo("$IN")`[0] @ broadcast lowest byte |
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veor $T,`&Dlo("$Qlo")`,`&Dlo("$Z")` |
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veor `&Dhi("$Z")`,`&Dlo("$R")` |
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vuzp.8 $Qlo,$Qhi |
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vsli.8 $Zo,$T,#1 @ compose the "carry" byte |
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vext.8 $Z,$zero,#1 @ Z>>=8 |
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vmull.p8 $R,$Zo,$mod @ "carry"·0xe1 |
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vshr.u8 $Zo,$T,#7 @ save Z's bottom bit |
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vext.8 $Qpost,$Qlo,$zero,#1 @ Qlo>>=8 |
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veor $Z,$Qhi |
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bne .Linner_neon |
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veor $Z,$Qpost @ modulo-scheduled artefact |
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vshl.i64 `&Dlo("$R")`,#48 |
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veor `&Dhi("$Z")`,`&Dlo("$R")` |
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@ finalization, normalize Z:Zo |
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vand $Zo,$mod @ suffices to mask the bit |
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vshr.u64 `&Dhi(&Q("$Zo"))`,`&Dlo("$Z")`,#63 |
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vshl.i64 $Z,#1 |
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subs $len,#16 |
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vorr $Z,`&Q("$Zo")` @ Z=Z:Zo<<1 |
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bne .Louter_neon |
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#ifdef __ARMEL__ |
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vrev64.8 $Z,$Z |
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#endif |
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sub $Xi,#16 |
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vst1.64 `&Dhi("$Z")`,[$Xi,:64]! @ write out Xi |
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vst1.64 `&Dlo("$Z")`,[$Xi,:64] |
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bx lr |
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.size gcm_ghash_neon,.-gcm_ghash_neon |
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#endif |
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___ |
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} |
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$code.=<<___; |
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.asciz "GHASH for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>" |
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.align 2 |
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___ |
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$code =~ s/\`([^\`]*)\`/eval $1/gem; |
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$code =~ s/\bbx\s+lr\b/.word\t0xe12fff1e/gm; # make it possible to compile with -march=armv4 |
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print $code; |
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close STDOUT; # enforce flush
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