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#!/usr/bin/env perl |
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# ==================================================================== |
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# Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL |
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# project. The module is, however, dual licensed under OpenSSL and |
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# CRYPTOGAMS licenses depending on where you obtain it. For further |
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# details see http://www.openssl.org/~appro/cryptogams/. |
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# ==================================================================== |
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# October 2005 |
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# |
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# "Teaser" Montgomery multiplication module for UltraSPARC. Why FPU? |
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# Because unlike integer multiplier, which simply stalls whole CPU, |
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# FPU is fully pipelined and can effectively emit 48 bit partial |
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# product every cycle. Why not blended SPARC v9? One can argue that |
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# making this module dependent on UltraSPARC VIS extension limits its |
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# binary compatibility. Well yes, it does exclude SPARC64 prior-V(!) |
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# implementations from compatibility matrix. But the rest, whole Sun |
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# UltraSPARC family and brand new Fujitsu's SPARC64 V, all support |
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# VIS extension instructions used in this module. This is considered |
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# good enough to not care about HAL SPARC64 users [if any] who have |
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# integer-only pure SPARCv9 module to "fall down" to. |
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# USI&II cores currently exhibit uniform 2x improvement [over pre- |
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# bn_mul_mont codebase] for all key lengths and benchmarks. On USIII |
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# performance improves few percents for shorter keys and worsens few |
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# percents for longer keys. This is because USIII integer multiplier |
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# is >3x faster than USI&II one, which is harder to match [but see |
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# TODO list below]. It should also be noted that SPARC64 V features |
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# out-of-order execution, which *might* mean that integer multiplier |
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# is pipelined, which in turn *might* be impossible to match... On |
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# additional note, SPARC64 V implements FP Multiply-Add instruction, |
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# which is perfectly usable in this context... In other words, as far |
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# as Fujitsu SPARC64 V goes, talk to the author:-) |
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# The implementation implies following "non-natural" limitations on |
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# input arguments: |
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# - num may not be less than 4; |
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# - num has to be even; |
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# Failure to meet either condition has no fatal effects, simply |
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# doesn't give any performance gain. |
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# TODO: |
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# - modulo-schedule inner loop for better performance (on in-order |
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# execution core such as UltraSPARC this shall result in further |
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# noticeable(!) improvement); |
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# - dedicated squaring procedure[?]; |
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###################################################################### |
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# November 2006 |
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# |
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# Modulo-scheduled inner loops allow to interleave floating point and |
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# integer instructions and minimize Read-After-Write penalties. This |
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# results in *further* 20-50% perfromance improvement [depending on |
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# key length, more for longer keys] on USI&II cores and 30-80% - on |
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# USIII&IV. |
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$fname="bn_mul_mont_fpu"; |
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$bits=32; |
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for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); } |
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if ($bits==64) { |
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$bias=2047; |
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$frame=192; |
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} else { |
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$bias=0; |
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$frame=128; # 96 rounded up to largest known cache-line |
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} |
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$locals=64; |
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# In order to provide for 32-/64-bit ABI duality, I keep integers wider |
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# than 32 bit in %g1-%g4 and %o0-%o5. %l0-%l7 and %i0-%i5 are used |
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# exclusively for pointers, indexes and other small values... |
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# int bn_mul_mont( |
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$rp="%i0"; # BN_ULONG *rp, |
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$ap="%i1"; # const BN_ULONG *ap, |
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$bp="%i2"; # const BN_ULONG *bp, |
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$np="%i3"; # const BN_ULONG *np, |
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$n0="%i4"; # const BN_ULONG *n0, |
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$num="%i5"; # int num); |
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$tp="%l0"; # t[num] |
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$ap_l="%l1"; # a[num],n[num] are smashed to 32-bit words and saved |
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$ap_h="%l2"; # to these four vectors as double-precision FP values. |
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$np_l="%l3"; # This way a bunch of fxtods are eliminated in second |
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$np_h="%l4"; # loop and L1-cache aliasing is minimized... |
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$i="%l5"; |
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$j="%l6"; |
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$mask="%l7"; # 16-bit mask, 0xffff |
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$n0="%g4"; # reassigned(!) to "64-bit" register |
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$carry="%i4"; # %i4 reused(!) for a carry bit |
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# FP register naming chart |
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# |
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# ..HILO |
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# dcba |
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# -------- |
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# LOa |
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# LOb |
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# LOc |
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# LOd |
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# HIa |
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# HIb |
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# HIc |
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# HId |
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# ..a |
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# ..b |
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$ba="%f0"; $bb="%f2"; $bc="%f4"; $bd="%f6"; |
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$na="%f8"; $nb="%f10"; $nc="%f12"; $nd="%f14"; |
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$alo="%f16"; $alo_="%f17"; $ahi="%f18"; $ahi_="%f19"; |
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$nlo="%f20"; $nlo_="%f21"; $nhi="%f22"; $nhi_="%f23"; |
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$dota="%f24"; $dotb="%f26"; |
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$aloa="%f32"; $alob="%f34"; $aloc="%f36"; $alod="%f38"; |
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$ahia="%f40"; $ahib="%f42"; $ahic="%f44"; $ahid="%f46"; |
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$nloa="%f48"; $nlob="%f50"; $nloc="%f52"; $nlod="%f54"; |
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$nhia="%f56"; $nhib="%f58"; $nhic="%f60"; $nhid="%f62"; |
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$ASI_FL16_P=0xD2; # magic ASI value to engage 16-bit FP load |
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$code=<<___; |
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.section ".text",#alloc,#execinstr |
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.global $fname |
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.align 32 |
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$fname: |
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save %sp,-$frame-$locals,%sp |
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cmp $num,4 |
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bl,a,pn %icc,.Lret |
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clr %i0 |
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andcc $num,1,%g0 ! $num has to be even... |
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bnz,a,pn %icc,.Lret |
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clr %i0 ! signal "unsupported input value" |
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srl $num,1,$num |
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sethi %hi(0xffff),$mask |
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ld [%i4+0],$n0 ! $n0 reassigned, remember? |
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or $mask,%lo(0xffff),$mask |
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ld [%i4+4],%o0 |
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sllx %o0,32,%o0 |
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or %o0,$n0,$n0 ! $n0=n0[1].n0[0] |
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sll $num,3,$num ! num*=8 |
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add %sp,$bias,%o0 ! real top of stack |
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sll $num,2,%o1 |
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add %o1,$num,%o1 ! %o1=num*5 |
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sub %o0,%o1,%o0 |
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and %o0,-2048,%o0 ! optimize TLB utilization |
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sub %o0,$bias,%sp ! alloca(5*num*8) |
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rd %asi,%o7 ! save %asi |
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add %sp,$bias+$frame+$locals,$tp |
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add $tp,$num,$ap_l |
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add $ap_l,$num,$ap_l ! [an]p_[lh] point at the vectors' ends ! |
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add $ap_l,$num,$ap_h |
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add $ap_h,$num,$np_l |
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add $np_l,$num,$np_h |
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wr %g0,$ASI_FL16_P,%asi ! setup %asi for 16-bit FP loads |
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add $rp,$num,$rp ! readjust input pointers to point |
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add $ap,$num,$ap ! at the ends too... |
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add $bp,$num,$bp |
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add $np,$num,$np |
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stx %o7,[%sp+$bias+$frame+48] ! save %asi |
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sub %g0,$num,$i ! i=-num |
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sub %g0,$num,$j ! j=-num |
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add $ap,$j,%o3 |
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add $bp,$i,%o4 |
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ld [%o3+4],%g1 ! bp[0] |
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ld [%o3+0],%o0 |
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ld [%o4+4],%g5 ! ap[0] |
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sllx %g1,32,%g1 |
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ld [%o4+0],%o1 |
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sllx %g5,32,%g5 |
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or %g1,%o0,%o0 |
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or %g5,%o1,%o1 |
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add $np,$j,%o5 |
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mulx %o1,%o0,%o0 ! ap[0]*bp[0] |
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mulx $n0,%o0,%o0 ! ap[0]*bp[0]*n0 |
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stx %o0,[%sp+$bias+$frame+0] |
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ld [%o3+0],$alo_ ! load a[j] as pair of 32-bit words |
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fzeros $alo |
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ld [%o3+4],$ahi_ |
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fzeros $ahi |
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ld [%o5+0],$nlo_ ! load n[j] as pair of 32-bit words |
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fzeros $nlo |
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ld [%o5+4],$nhi_ |
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fzeros $nhi |
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! transfer b[i] to FPU as 4x16-bit values |
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ldda [%o4+2]%asi,$ba |
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fxtod $alo,$alo |
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ldda [%o4+0]%asi,$bb |
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fxtod $ahi,$ahi |
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ldda [%o4+6]%asi,$bc |
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fxtod $nlo,$nlo |
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ldda [%o4+4]%asi,$bd |
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fxtod $nhi,$nhi |
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! transfer ap[0]*b[0]*n0 to FPU as 4x16-bit values |
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ldda [%sp+$bias+$frame+6]%asi,$na |
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fxtod $ba,$ba |
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ldda [%sp+$bias+$frame+4]%asi,$nb |
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fxtod $bb,$bb |
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ldda [%sp+$bias+$frame+2]%asi,$nc |
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fxtod $bc,$bc |
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ldda [%sp+$bias+$frame+0]%asi,$nd |
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fxtod $bd,$bd |
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std $alo,[$ap_l+$j] ! save smashed ap[j] in double format |
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fxtod $na,$na |
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std $ahi,[$ap_h+$j] |
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fxtod $nb,$nb |
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std $nlo,[$np_l+$j] ! save smashed np[j] in double format |
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fxtod $nc,$nc |
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std $nhi,[$np_h+$j] |
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fxtod $nd,$nd |
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fmuld $alo,$ba,$aloa |
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fmuld $nlo,$na,$nloa |
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fmuld $alo,$bb,$alob |
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fmuld $nlo,$nb,$nlob |
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fmuld $alo,$bc,$aloc |
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faddd $aloa,$nloa,$nloa |
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fmuld $nlo,$nc,$nloc |
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fmuld $alo,$bd,$alod |
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faddd $alob,$nlob,$nlob |
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fmuld $nlo,$nd,$nlod |
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fmuld $ahi,$ba,$ahia |
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faddd $aloc,$nloc,$nloc |
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fmuld $nhi,$na,$nhia |
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fmuld $ahi,$bb,$ahib |
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faddd $alod,$nlod,$nlod |
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fmuld $nhi,$nb,$nhib |
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fmuld $ahi,$bc,$ahic |
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faddd $ahia,$nhia,$nhia |
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fmuld $nhi,$nc,$nhic |
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fmuld $ahi,$bd,$ahid |
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faddd $ahib,$nhib,$nhib |
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fmuld $nhi,$nd,$nhid |
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faddd $ahic,$nhic,$dota ! $nhic |
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faddd $ahid,$nhid,$dotb ! $nhid |
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faddd $nloc,$nhia,$nloc |
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faddd $nlod,$nhib,$nlod |
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fdtox $nloa,$nloa |
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fdtox $nlob,$nlob |
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fdtox $nloc,$nloc |
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fdtox $nlod,$nlod |
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std $nloa,[%sp+$bias+$frame+0] |
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add $j,8,$j |
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std $nlob,[%sp+$bias+$frame+8] |
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add $ap,$j,%o4 |
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std $nloc,[%sp+$bias+$frame+16] |
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add $np,$j,%o5 |
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std $nlod,[%sp+$bias+$frame+24] |
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ld [%o4+0],$alo_ ! load a[j] as pair of 32-bit words |
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fzeros $alo |
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ld [%o4+4],$ahi_ |
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fzeros $ahi |
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ld [%o5+0],$nlo_ ! load n[j] as pair of 32-bit words |
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fzeros $nlo |
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ld [%o5+4],$nhi_ |
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fzeros $nhi |
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fxtod $alo,$alo |
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fxtod $ahi,$ahi |
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fxtod $nlo,$nlo |
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fxtod $nhi,$nhi |
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ldx [%sp+$bias+$frame+0],%o0 |
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fmuld $alo,$ba,$aloa |
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ldx [%sp+$bias+$frame+8],%o1 |
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fmuld $nlo,$na,$nloa |
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ldx [%sp+$bias+$frame+16],%o2 |
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fmuld $alo,$bb,$alob |
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ldx [%sp+$bias+$frame+24],%o3 |
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fmuld $nlo,$nb,$nlob |
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srlx %o0,16,%o7 |
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std $alo,[$ap_l+$j] ! save smashed ap[j] in double format |
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fmuld $alo,$bc,$aloc |
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add %o7,%o1,%o1 |
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std $ahi,[$ap_h+$j] |
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faddd $aloa,$nloa,$nloa |
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fmuld $nlo,$nc,$nloc |
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srlx %o1,16,%o7 |
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std $nlo,[$np_l+$j] ! save smashed np[j] in double format |
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fmuld $alo,$bd,$alod |
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add %o7,%o2,%o2 |
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std $nhi,[$np_h+$j] |
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faddd $alob,$nlob,$nlob |
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fmuld $nlo,$nd,$nlod |
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srlx %o2,16,%o7 |
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fmuld $ahi,$ba,$ahia |
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add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15] |
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faddd $aloc,$nloc,$nloc |
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fmuld $nhi,$na,$nhia |
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!and %o0,$mask,%o0 |
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!and %o1,$mask,%o1 |
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!and %o2,$mask,%o2 |
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!sllx %o1,16,%o1 |
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!sllx %o2,32,%o2 |
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!sllx %o3,48,%o7 |
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!or %o1,%o0,%o0 |
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!or %o2,%o0,%o0 |
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!or %o7,%o0,%o0 ! 64-bit result |
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srlx %o3,16,%g1 ! 34-bit carry |
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fmuld $ahi,$bb,$ahib |
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faddd $alod,$nlod,$nlod |
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fmuld $nhi,$nb,$nhib |
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fmuld $ahi,$bc,$ahic |
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faddd $ahia,$nhia,$nhia |
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fmuld $nhi,$nc,$nhic |
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fmuld $ahi,$bd,$ahid |
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faddd $ahib,$nhib,$nhib |
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fmuld $nhi,$nd,$nhid |
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faddd $dota,$nloa,$nloa |
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faddd $dotb,$nlob,$nlob |
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faddd $ahic,$nhic,$dota ! $nhic |
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faddd $ahid,$nhid,$dotb ! $nhid |
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faddd $nloc,$nhia,$nloc |
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faddd $nlod,$nhib,$nlod |
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fdtox $nloa,$nloa |
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fdtox $nlob,$nlob |
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fdtox $nloc,$nloc |
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fdtox $nlod,$nlod |
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std $nloa,[%sp+$bias+$frame+0] |
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std $nlob,[%sp+$bias+$frame+8] |
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addcc $j,8,$j |
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std $nloc,[%sp+$bias+$frame+16] |
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bz,pn %icc,.L1stskip |
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std $nlod,[%sp+$bias+$frame+24] |
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.align 32 ! incidentally already aligned ! |
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.L1st: |
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add $ap,$j,%o4 |
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add $np,$j,%o5 |
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ld [%o4+0],$alo_ ! load a[j] as pair of 32-bit words |
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fzeros $alo |
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ld [%o4+4],$ahi_ |
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fzeros $ahi |
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ld [%o5+0],$nlo_ ! load n[j] as pair of 32-bit words |
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fzeros $nlo |
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ld [%o5+4],$nhi_ |
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fzeros $nhi |
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fxtod $alo,$alo |
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fxtod $ahi,$ahi |
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fxtod $nlo,$nlo |
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fxtod $nhi,$nhi |
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ldx [%sp+$bias+$frame+0],%o0 |
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fmuld $alo,$ba,$aloa |
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ldx [%sp+$bias+$frame+8],%o1 |
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fmuld $nlo,$na,$nloa |
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ldx [%sp+$bias+$frame+16],%o2 |
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fmuld $alo,$bb,$alob |
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ldx [%sp+$bias+$frame+24],%o3 |
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fmuld $nlo,$nb,$nlob |
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srlx %o0,16,%o7 |
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std $alo,[$ap_l+$j] ! save smashed ap[j] in double format |
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fmuld $alo,$bc,$aloc |
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add %o7,%o1,%o1 |
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std $ahi,[$ap_h+$j] |
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faddd $aloa,$nloa,$nloa |
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fmuld $nlo,$nc,$nloc |
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srlx %o1,16,%o7 |
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std $nlo,[$np_l+$j] ! save smashed np[j] in double format |
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fmuld $alo,$bd,$alod |
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add %o7,%o2,%o2 |
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std $nhi,[$np_h+$j] |
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faddd $alob,$nlob,$nlob |
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fmuld $nlo,$nd,$nlod |
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srlx %o2,16,%o7 |
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fmuld $ahi,$ba,$ahia |
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add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15] |
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and %o0,$mask,%o0 |
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faddd $aloc,$nloc,$nloc |
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fmuld $nhi,$na,$nhia |
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and %o1,$mask,%o1 |
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and %o2,$mask,%o2 |
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fmuld $ahi,$bb,$ahib |
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sllx %o1,16,%o1 |
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faddd $alod,$nlod,$nlod |
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fmuld $nhi,$nb,$nhib |
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sllx %o2,32,%o2 |
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fmuld $ahi,$bc,$ahic |
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sllx %o3,48,%o7 |
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or %o1,%o0,%o0 |
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faddd $ahia,$nhia,$nhia |
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fmuld $nhi,$nc,$nhic |
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or %o2,%o0,%o0 |
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fmuld $ahi,$bd,$ahid |
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or %o7,%o0,%o0 ! 64-bit result |
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faddd $ahib,$nhib,$nhib |
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fmuld $nhi,$nd,$nhid |
|
|
addcc %g1,%o0,%o0 |
|
|
faddd $dota,$nloa,$nloa |
|
|
srlx %o3,16,%g1 ! 34-bit carry |
|
|
faddd $dotb,$nlob,$nlob |
|
|
bcs,a %xcc,.+8 |
|
|
add %g1,1,%g1 |
|
|
|
|
|
stx %o0,[$tp] ! tp[j-1]= |
|
|
|
|
|
faddd $ahic,$nhic,$dota ! $nhic |
|
|
faddd $ahid,$nhid,$dotb ! $nhid |
|
|
|
|
|
faddd $nloc,$nhia,$nloc |
|
|
faddd $nlod,$nhib,$nlod |
|
|
|
|
|
fdtox $nloa,$nloa |
|
|
fdtox $nlob,$nlob |
|
|
fdtox $nloc,$nloc |
|
|
fdtox $nlod,$nlod |
|
|
|
|
|
std $nloa,[%sp+$bias+$frame+0] |
|
|
std $nlob,[%sp+$bias+$frame+8] |
|
|
std $nloc,[%sp+$bias+$frame+16] |
|
|
std $nlod,[%sp+$bias+$frame+24] |
|
|
|
|
|
addcc $j,8,$j |
|
|
bnz,pt %icc,.L1st |
|
|
add $tp,8,$tp |
|
|
|
|
|
.L1stskip: |
|
|
fdtox $dota,$dota |
|
|
fdtox $dotb,$dotb |
|
|
|
|
|
ldx [%sp+$bias+$frame+0],%o0 |
|
|
ldx [%sp+$bias+$frame+8],%o1 |
|
|
ldx [%sp+$bias+$frame+16],%o2 |
|
|
ldx [%sp+$bias+$frame+24],%o3 |
|
|
|
|
|
srlx %o0,16,%o7 |
|
|
std $dota,[%sp+$bias+$frame+32] |
|
|
add %o7,%o1,%o1 |
|
|
std $dotb,[%sp+$bias+$frame+40] |
|
|
srlx %o1,16,%o7 |
|
|
add %o7,%o2,%o2 |
|
|
srlx %o2,16,%o7 |
|
|
add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15] |
|
|
and %o0,$mask,%o0 |
|
|
and %o1,$mask,%o1 |
|
|
and %o2,$mask,%o2 |
|
|
sllx %o1,16,%o1 |
|
|
sllx %o2,32,%o2 |
|
|
sllx %o3,48,%o7 |
|
|
or %o1,%o0,%o0 |
|
|
or %o2,%o0,%o0 |
|
|
or %o7,%o0,%o0 ! 64-bit result |
|
|
ldx [%sp+$bias+$frame+32],%o4 |
|
|
addcc %g1,%o0,%o0 |
|
|
ldx [%sp+$bias+$frame+40],%o5 |
|
|
srlx %o3,16,%g1 ! 34-bit carry |
|
|
bcs,a %xcc,.+8 |
|
|
add %g1,1,%g1 |
|
|
|
|
|
stx %o0,[$tp] ! tp[j-1]= |
|
|
add $tp,8,$tp |
|
|
|
|
|
srlx %o4,16,%o7 |
|
|
add %o7,%o5,%o5 |
|
|
and %o4,$mask,%o4 |
|
|
sllx %o5,16,%o7 |
|
|
or %o7,%o4,%o4 |
|
|
addcc %g1,%o4,%o4 |
|
|
srlx %o5,48,%g1 |
|
|
bcs,a %xcc,.+8 |
|
|
add %g1,1,%g1 |
|
|
|
|
|
mov %g1,$carry |
|
|
stx %o4,[$tp] ! tp[num-1]= |
|
|
|
|
|
ba .Louter |
|
|
add $i,8,$i |
|
|
.align 32 |
|
|
.Louter: |
|
|
sub %g0,$num,$j ! j=-num |
|
|
add %sp,$bias+$frame+$locals,$tp |
|
|
|
|
|
add $ap,$j,%o3 |
|
|
add $bp,$i,%o4 |
|
|
|
|
|
ld [%o3+4],%g1 ! bp[i] |
|
|
ld [%o3+0],%o0 |
|
|
ld [%o4+4],%g5 ! ap[0] |
|
|
sllx %g1,32,%g1 |
|
|
ld [%o4+0],%o1 |
|
|
sllx %g5,32,%g5 |
|
|
or %g1,%o0,%o0 |
|
|
or %g5,%o1,%o1 |
|
|
|
|
|
ldx [$tp],%o2 ! tp[0] |
|
|
mulx %o1,%o0,%o0 |
|
|
addcc %o2,%o0,%o0 |
|
|
mulx $n0,%o0,%o0 ! (ap[0]*bp[i]+t[0])*n0 |
|
|
stx %o0,[%sp+$bias+$frame+0] |
|
|
|
|
|
! transfer b[i] to FPU as 4x16-bit values |
|
|
ldda [%o4+2]%asi,$ba |
|
|
ldda [%o4+0]%asi,$bb |
|
|
ldda [%o4+6]%asi,$bc |
|
|
ldda [%o4+4]%asi,$bd |
|
|
|
|
|
! transfer (ap[0]*b[i]+t[0])*n0 to FPU as 4x16-bit values |
|
|
ldda [%sp+$bias+$frame+6]%asi,$na |
|
|
fxtod $ba,$ba |
|
|
ldda [%sp+$bias+$frame+4]%asi,$nb |
|
|
fxtod $bb,$bb |
|
|
ldda [%sp+$bias+$frame+2]%asi,$nc |
|
|
fxtod $bc,$bc |
|
|
ldda [%sp+$bias+$frame+0]%asi,$nd |
|
|
fxtod $bd,$bd |
|
|
ldd [$ap_l+$j],$alo ! load a[j] in double format |
|
|
fxtod $na,$na |
|
|
ldd [$ap_h+$j],$ahi |
|
|
fxtod $nb,$nb |
|
|
ldd [$np_l+$j],$nlo ! load n[j] in double format |
|
|
fxtod $nc,$nc |
|
|
ldd [$np_h+$j],$nhi |
|
|
fxtod $nd,$nd |
|
|
|
|
|
fmuld $alo,$ba,$aloa |
|
|
fmuld $nlo,$na,$nloa |
|
|
fmuld $alo,$bb,$alob |
|
|
fmuld $nlo,$nb,$nlob |
|
|
fmuld $alo,$bc,$aloc |
|
|
faddd $aloa,$nloa,$nloa |
|
|
fmuld $nlo,$nc,$nloc |
|
|
fmuld $alo,$bd,$alod |
|
|
faddd $alob,$nlob,$nlob |
|
|
fmuld $nlo,$nd,$nlod |
|
|
fmuld $ahi,$ba,$ahia |
|
|
faddd $aloc,$nloc,$nloc |
|
|
fmuld $nhi,$na,$nhia |
|
|
fmuld $ahi,$bb,$ahib |
|
|
faddd $alod,$nlod,$nlod |
|
|
fmuld $nhi,$nb,$nhib |
|
|
fmuld $ahi,$bc,$ahic |
|
|
faddd $ahia,$nhia,$nhia |
|
|
fmuld $nhi,$nc,$nhic |
|
|
fmuld $ahi,$bd,$ahid |
|
|
faddd $ahib,$nhib,$nhib |
|
|
fmuld $nhi,$nd,$nhid |
|
|
|
|
|
faddd $ahic,$nhic,$dota ! $nhic |
|
|
faddd $ahid,$nhid,$dotb ! $nhid |
|
|
|
|
|
faddd $nloc,$nhia,$nloc |
|
|
faddd $nlod,$nhib,$nlod |
|
|
|
|
|
fdtox $nloa,$nloa |
|
|
fdtox $nlob,$nlob |
|
|
fdtox $nloc,$nloc |
|
|
fdtox $nlod,$nlod |
|
|
|
|
|
std $nloa,[%sp+$bias+$frame+0] |
|
|
std $nlob,[%sp+$bias+$frame+8] |
|
|
std $nloc,[%sp+$bias+$frame+16] |
|
|
add $j,8,$j |
|
|
std $nlod,[%sp+$bias+$frame+24] |
|
|
|
|
|
ldd [$ap_l+$j],$alo ! load a[j] in double format |
|
|
ldd [$ap_h+$j],$ahi |
|
|
ldd [$np_l+$j],$nlo ! load n[j] in double format |
|
|
ldd [$np_h+$j],$nhi |
|
|
|
|
|
fmuld $alo,$ba,$aloa |
|
|
fmuld $nlo,$na,$nloa |
|
|
fmuld $alo,$bb,$alob |
|
|
fmuld $nlo,$nb,$nlob |
|
|
fmuld $alo,$bc,$aloc |
|
|
ldx [%sp+$bias+$frame+0],%o0 |
|
|
faddd $aloa,$nloa,$nloa |
|
|
fmuld $nlo,$nc,$nloc |
|
|
ldx [%sp+$bias+$frame+8],%o1 |
|
|
fmuld $alo,$bd,$alod |
|
|
ldx [%sp+$bias+$frame+16],%o2 |
|
|
faddd $alob,$nlob,$nlob |
|
|
fmuld $nlo,$nd,$nlod |
|
|
ldx [%sp+$bias+$frame+24],%o3 |
|
|
fmuld $ahi,$ba,$ahia |
|
|
|
|
|
srlx %o0,16,%o7 |
|
|
faddd $aloc,$nloc,$nloc |
|
|
fmuld $nhi,$na,$nhia |
|
|
add %o7,%o1,%o1 |
|
|
fmuld $ahi,$bb,$ahib |
|
|
srlx %o1,16,%o7 |
|
|
faddd $alod,$nlod,$nlod |
|
|
fmuld $nhi,$nb,$nhib |
|
|
add %o7,%o2,%o2 |
|
|
fmuld $ahi,$bc,$ahic |
|
|
srlx %o2,16,%o7 |
|
|
faddd $ahia,$nhia,$nhia |
|
|
fmuld $nhi,$nc,$nhic |
|
|
add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15] |
|
|
! why? |
|
|
and %o0,$mask,%o0 |
|
|
fmuld $ahi,$bd,$ahid |
|
|
and %o1,$mask,%o1 |
|
|
and %o2,$mask,%o2 |
|
|
faddd $ahib,$nhib,$nhib |
|
|
fmuld $nhi,$nd,$nhid |
|
|
sllx %o1,16,%o1 |
|
|
faddd $dota,$nloa,$nloa |
|
|
sllx %o2,32,%o2 |
|
|
faddd $dotb,$nlob,$nlob |
|
|
sllx %o3,48,%o7 |
|
|
or %o1,%o0,%o0 |
|
|
faddd $ahic,$nhic,$dota ! $nhic |
|
|
or %o2,%o0,%o0 |
|
|
faddd $ahid,$nhid,$dotb ! $nhid |
|
|
or %o7,%o0,%o0 ! 64-bit result |
|
|
ldx [$tp],%o7 |
|
|
faddd $nloc,$nhia,$nloc |
|
|
addcc %o7,%o0,%o0 |
|
|
! end-of-why? |
|
|
faddd $nlod,$nhib,$nlod |
|
|
srlx %o3,16,%g1 ! 34-bit carry |
|
|
fdtox $nloa,$nloa |
|
|
bcs,a %xcc,.+8 |
|
|
add %g1,1,%g1 |
|
|
|
|
|
fdtox $nlob,$nlob |
|
|
fdtox $nloc,$nloc |
|
|
fdtox $nlod,$nlod |
|
|
|
|
|
std $nloa,[%sp+$bias+$frame+0] |
|
|
std $nlob,[%sp+$bias+$frame+8] |
|
|
addcc $j,8,$j |
|
|
std $nloc,[%sp+$bias+$frame+16] |
|
|
bz,pn %icc,.Linnerskip |
|
|
std $nlod,[%sp+$bias+$frame+24] |
|
|
|
|
|
ba .Linner |
|
|
nop |
|
|
.align 32 |
|
|
.Linner: |
|
|
ldd [$ap_l+$j],$alo ! load a[j] in double format |
|
|
ldd [$ap_h+$j],$ahi |
|
|
ldd [$np_l+$j],$nlo ! load n[j] in double format |
|
|
ldd [$np_h+$j],$nhi |
|
|
|
|
|
fmuld $alo,$ba,$aloa |
|
|
fmuld $nlo,$na,$nloa |
|
|
fmuld $alo,$bb,$alob |
|
|
fmuld $nlo,$nb,$nlob |
|
|
fmuld $alo,$bc,$aloc |
|
|
ldx [%sp+$bias+$frame+0],%o0 |
|
|
faddd $aloa,$nloa,$nloa |
|
|
fmuld $nlo,$nc,$nloc |
|
|
ldx [%sp+$bias+$frame+8],%o1 |
|
|
fmuld $alo,$bd,$alod |
|
|
ldx [%sp+$bias+$frame+16],%o2 |
|
|
faddd $alob,$nlob,$nlob |
|
|
fmuld $nlo,$nd,$nlod |
|
|
ldx [%sp+$bias+$frame+24],%o3 |
|
|
fmuld $ahi,$ba,$ahia |
|
|
|
|
|
srlx %o0,16,%o7 |
|
|
faddd $aloc,$nloc,$nloc |
|
|
fmuld $nhi,$na,$nhia |
|
|
add %o7,%o1,%o1 |
|
|
fmuld $ahi,$bb,$ahib |
|
|
srlx %o1,16,%o7 |
|
|
faddd $alod,$nlod,$nlod |
|
|
fmuld $nhi,$nb,$nhib |
|
|
add %o7,%o2,%o2 |
|
|
fmuld $ahi,$bc,$ahic |
|
|
srlx %o2,16,%o7 |
|
|
faddd $ahia,$nhia,$nhia |
|
|
fmuld $nhi,$nc,$nhic |
|
|
add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15] |
|
|
and %o0,$mask,%o0 |
|
|
fmuld $ahi,$bd,$ahid |
|
|
and %o1,$mask,%o1 |
|
|
and %o2,$mask,%o2 |
|
|
faddd $ahib,$nhib,$nhib |
|
|
fmuld $nhi,$nd,$nhid |
|
|
sllx %o1,16,%o1 |
|
|
faddd $dota,$nloa,$nloa |
|
|
sllx %o2,32,%o2 |
|
|
faddd $dotb,$nlob,$nlob |
|
|
sllx %o3,48,%o7 |
|
|
or %o1,%o0,%o0 |
|
|
faddd $ahic,$nhic,$dota ! $nhic |
|
|
or %o2,%o0,%o0 |
|
|
faddd $ahid,$nhid,$dotb ! $nhid |
|
|
or %o7,%o0,%o0 ! 64-bit result |
|
|
faddd $nloc,$nhia,$nloc |
|
|
addcc %g1,%o0,%o0 |
|
|
ldx [$tp+8],%o7 ! tp[j] |
|
|
faddd $nlod,$nhib,$nlod |
|
|
srlx %o3,16,%g1 ! 34-bit carry |
|
|
fdtox $nloa,$nloa |
|
|
bcs,a %xcc,.+8 |
|
|
add %g1,1,%g1 |
|
|
fdtox $nlob,$nlob |
|
|
addcc %o7,%o0,%o0 |
|
|
fdtox $nloc,$nloc |
|
|
bcs,a %xcc,.+8 |
|
|
add %g1,1,%g1 |
|
|
|
|
|
stx %o0,[$tp] ! tp[j-1] |
|
|
fdtox $nlod,$nlod |
|
|
|
|
|
std $nloa,[%sp+$bias+$frame+0] |
|
|
std $nlob,[%sp+$bias+$frame+8] |
|
|
std $nloc,[%sp+$bias+$frame+16] |
|
|
addcc $j,8,$j |
|
|
std $nlod,[%sp+$bias+$frame+24] |
|
|
bnz,pt %icc,.Linner |
|
|
add $tp,8,$tp |
|
|
|
|
|
.Linnerskip: |
|
|
fdtox $dota,$dota |
|
|
fdtox $dotb,$dotb |
|
|
|
|
|
ldx [%sp+$bias+$frame+0],%o0 |
|
|
ldx [%sp+$bias+$frame+8],%o1 |
|
|
ldx [%sp+$bias+$frame+16],%o2 |
|
|
ldx [%sp+$bias+$frame+24],%o3 |
|
|
|
|
|
srlx %o0,16,%o7 |
|
|
std $dota,[%sp+$bias+$frame+32] |
|
|
add %o7,%o1,%o1 |
|
|
std $dotb,[%sp+$bias+$frame+40] |
|
|
srlx %o1,16,%o7 |
|
|
add %o7,%o2,%o2 |
|
|
srlx %o2,16,%o7 |
|
|
add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15] |
|
|
and %o0,$mask,%o0 |
|
|
and %o1,$mask,%o1 |
|
|
and %o2,$mask,%o2 |
|
|
sllx %o1,16,%o1 |
|
|
sllx %o2,32,%o2 |
|
|
sllx %o3,48,%o7 |
|
|
or %o1,%o0,%o0 |
|
|
or %o2,%o0,%o0 |
|
|
ldx [%sp+$bias+$frame+32],%o4 |
|
|
or %o7,%o0,%o0 ! 64-bit result |
|
|
ldx [%sp+$bias+$frame+40],%o5 |
|
|
addcc %g1,%o0,%o0 |
|
|
ldx [$tp+8],%o7 ! tp[j] |
|
|
srlx %o3,16,%g1 ! 34-bit carry |
|
|
bcs,a %xcc,.+8 |
|
|
add %g1,1,%g1 |
|
|
|
|
|
addcc %o7,%o0,%o0 |
|
|
bcs,a %xcc,.+8 |
|
|
add %g1,1,%g1 |
|
|
|
|
|
stx %o0,[$tp] ! tp[j-1] |
|
|
add $tp,8,$tp |
|
|
|
|
|
srlx %o4,16,%o7 |
|
|
add %o7,%o5,%o5 |
|
|
and %o4,$mask,%o4 |
|
|
sllx %o5,16,%o7 |
|
|
or %o7,%o4,%o4 |
|
|
addcc %g1,%o4,%o4 |
|
|
srlx %o5,48,%g1 |
|
|
bcs,a %xcc,.+8 |
|
|
add %g1,1,%g1 |
|
|
|
|
|
addcc $carry,%o4,%o4 |
|
|
stx %o4,[$tp] ! tp[num-1] |
|
|
mov %g1,$carry |
|
|
bcs,a %xcc,.+8 |
|
|
add $carry,1,$carry |
|
|
|
|
|
addcc $i,8,$i |
|
|
bnz %icc,.Louter |
|
|
nop |
|
|
|
|
|
add $tp,8,$tp ! adjust tp to point at the end |
|
|
orn %g0,%g0,%g4 |
|
|
sub %g0,$num,%o7 ! n=-num |
|
|
ba .Lsub |
|
|
subcc %g0,%g0,%g0 ! clear %icc.c |
|
|
|
|
|
.align 32 |
|
|
.Lsub: |
|
|
ldx [$tp+%o7],%o0 |
|
|
add $np,%o7,%g1 |
|
|
ld [%g1+0],%o2 |
|
|
ld [%g1+4],%o3 |
|
|
srlx %o0,32,%o1 |
|
|
subccc %o0,%o2,%o2 |
|
|
add $rp,%o7,%g1 |
|
|
subccc %o1,%o3,%o3 |
|
|
st %o2,[%g1+0] |
|
|
add %o7,8,%o7 |
|
|
brnz,pt %o7,.Lsub |
|
|
st %o3,[%g1+4] |
|
|
subc $carry,0,%g4 |
|
|
sub %g0,$num,%o7 ! n=-num |
|
|
ba .Lcopy |
|
|
nop |
|
|
|
|
|
.align 32 |
|
|
.Lcopy: |
|
|
ldx [$tp+%o7],%o0 |
|
|
add $rp,%o7,%g1 |
|
|
ld [%g1+0],%o2 |
|
|
ld [%g1+4],%o3 |
|
|
stx %g0,[$tp+%o7] |
|
|
and %o0,%g4,%o0 |
|
|
srlx %o0,32,%o1 |
|
|
andn %o2,%g4,%o2 |
|
|
andn %o3,%g4,%o3 |
|
|
or %o2,%o0,%o0 |
|
|
or %o3,%o1,%o1 |
|
|
st %o0,[%g1+0] |
|
|
add %o7,8,%o7 |
|
|
brnz,pt %o7,.Lcopy |
|
|
st %o1,[%g1+4] |
|
|
sub %g0,$num,%o7 ! n=-num |
|
|
|
|
|
.Lzap: |
|
|
stx %g0,[$ap_l+%o7] |
|
|
stx %g0,[$ap_h+%o7] |
|
|
stx %g0,[$np_l+%o7] |
|
|
stx %g0,[$np_h+%o7] |
|
|
add %o7,8,%o7 |
|
|
brnz,pt %o7,.Lzap |
|
|
nop |
|
|
|
|
|
ldx [%sp+$bias+$frame+48],%o7 |
|
|
wr %g0,%o7,%asi ! restore %asi |
|
|
|
|
|
mov 1,%i0 |
|
|
.Lret: |
|
|
ret |
|
|
restore |
|
|
.type $fname,#function |
|
|
.size $fname,(.-$fname) |
|
|
.asciz "Montgomery Multipltication for UltraSPARC, CRYPTOGAMS by <appro\@openssl.org>" |
|
|
.align 32 |
|
|
___ |
|
|
|
|
|
$code =~ s/\`([^\`]*)\`/eval($1)/gem; |
|
|
|
|
|
# Below substitution makes it possible to compile without demanding |
|
|
# VIS extentions on command line, e.g. -xarch=v9 vs. -xarch=v9a. I |
|
|
# dare to do this, because VIS capability is detected at run-time now |
|
|
# and this routine is not called on CPU not capable to execute it. Do |
|
|
# note that fzeros is not the only VIS dependency! Another dependency |
|
|
# is implicit and is just _a_ numerical value loaded to %asi register, |
|
|
# which assembler can't recognize as VIS specific... |
|
|
$code =~ s/fzeros\s+%f([0-9]+)/ |
|
|
sprintf(".word\t0x%x\t! fzeros %%f%d",0x81b00c20|($1<<25),$1) |
|
|
/gem; |
|
|
|
|
|
print $code; |
|
|
# flush |
|
|
close STDOUT;
|
|
|
|