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@ -276,8 +276,7 @@ static int libztex_configureFpgaHS(struct libztex_device *ztex, const char* firm
@@ -276,8 +276,7 @@ static int libztex_configureFpgaHS(struct libztex_device *ztex, const char* firm
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struct libztex_fpgastate state; |
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const int transactionBytes = 65536; |
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unsigned char buf[transactionBytes], settings[2]; |
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int tries, cnt, buf_p, i; |
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ssize_t pos = 0; |
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int tries, cnt, err, i; |
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FILE *fp; |
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if (!libztex_checkCapability(ztex, CAPABILITY_HS_FPGA)) |
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@ -302,52 +301,25 @@ static int libztex_configureFpgaHS(struct libztex_device *ztex, const char* firm
@@ -302,52 +301,25 @@ static int libztex_configureFpgaHS(struct libztex_device *ztex, const char* firm
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return -2; |
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} |
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while (pos < transactionBytes && !feof(fp)) { |
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buf[pos++] = getc(fp); |
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} |
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if (feof(fp)) |
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pos--; |
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if (bs != 0 && bs != 1) |
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bs = libztex_detectBitstreamBitOrder(buf, transactionBytes < pos? transactionBytes: pos); |
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if (bs == 1) |
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libztex_swapBits(buf, pos); |
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libusb_control_transfer(ztex->hndl, 0x40, 0x34, 0, 0, NULL, 0, 1000); |
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// 0x34 - initHSFPGAConfiguration
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buf_p = pos; |
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while (1) { |
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i = 0; |
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while (i < buf_p) { |
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if (libusb_bulk_transfer(ztex->hndl, |
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settings[0], |
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&buf[i], |
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buf_p - i, |
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&cnt, 1000) != 0) { |
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applog(LOG_ERR, "%s: Failed send hs fpga data", ztex->repr); |
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break; |
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} |
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usleep(500); |
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i += cnt; |
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} |
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if (i < buf_p || buf_p < transactionBytes) |
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break; |
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buf_p = 0; |
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while (buf_p < transactionBytes && !feof(fp)) { |
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buf[buf_p++] = getc(fp); |
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} |
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if (feof(fp)) |
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buf_p--; |
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pos += buf_p; |
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if (buf_p == 0) |
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break; |
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do |
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{ |
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int length = fread(buf,1,transactionBytes,fp); |
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if (bs != 0 && bs != 1) |
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bs = libztex_detectBitstreamBitOrder(buf, length); |
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if (bs == 1) |
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libztex_swapBits(buf, buf_p); |
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libztex_swapBits(buf, length); |
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err = libusb_bulk_transfer(ztex->hndl, settings[0], buf, length, &cnt, 1000); |
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if (cnt != length) |
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applog(LOG_ERR, "%s: cnt != length", ztex->repr); |
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if (err != 0) |
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applog(LOG_ERR, "%s: Failed send hs fpga data", ztex->repr); |
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} |
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while (!feof(fp)); |
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libusb_control_transfer(ztex->hndl, 0x40, 0x35, 0, 0, NULL, 0, 1000); |
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// 0x35 - finishHSFPGAConfiguration
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