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Move phatk kernel to offset vector based nonce bases as well.
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@ -819,7 +819,7 @@ static cl_int queue_phatk_kernel(_clState *clState, dev_blk_ctx *blk,
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nonces = alloca(sizeof(uint) * vwidth);
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for (i = 0; i < vwidth; i++)
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nonces[i] = blk->nonce + i;
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nonces[i] = blk->nonce + (i * threads);
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CL_SET_VARG(vwidth, nonces);
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CL_SET_BLKARG(W16);
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@ -168,8 +168,8 @@ void search( const uint state0, const uint state1, const uint state2, const uint
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{
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u W[124];
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u Vals[8];
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u W[132];
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u *Vals=&W[124];
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//Dummy Variable to prevent compiler from reordering between rounds
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u t1;
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@ -186,23 +186,11 @@ void search( const uint state0, const uint state1, const uint state2, const uint
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W[16] = W16;
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W[17] = W17;
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#ifdef VECTORS4
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//Less dependencies to get both the local id and group id and then add them
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W[3] = base + (uint)(get_local_id(0)) * 4u + (uint)(get_group_id(0)) * (WORKSIZE * 4u);
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uint r = rot(W[3].x,25u)^rot(W[3].x,14u)^((W[3].x)>>3U);
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//Since only the 2 LSB is opposite between the nonces, we can save an instruction by flipping the 4 bits in W18 rather than the 1 bit in W3
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W[18] = PreW18 + (u){r, r ^ 0x2004000U, r ^ 0x4008000U, r ^ 0x600C000U};
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#elif defined VECTORS2
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W[3] = base + (uint)(get_local_id(0)) * 2u + (uint)(get_group_id(0)) * (WORKSIZE * 2u);
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uint r = rot(W[3].x,25u)^rot(W[3].x,14u)^((W[3].x)>>3U);
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W[18] = PreW18 + (u){r, r ^ 0x2004000U};
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#else
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W[3] = base + get_local_id(0) + get_group_id(0) * (WORKSIZE);
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W[3] = base + (uint)get_global_id(0);
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u r = rot(W[3],25u)^rot(W[3],14u)^((W[3])>>3U);
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W[18] = PreW18 + r;
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#endif
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//the order of the W calcs and Rounds is like this because the compiler needs help finding how to order the instructions
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//the order of the W calcs and Rounds is like this because the compiler needs help finding how to order the instructions
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Vals[4] = PreVal4 + W[3];
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