mirror of
https://github.com/GOSTSec/ccminer
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9eead77027
This will allow later more gpu candidates. Note: This is an unfinished work, we keep the previous behavior for now To finish this, all algos solutions should be migrated and submitted nonces attributes stored. Its required to handle the different share diff per nonce and fix the possible solved count error (if 1/2 nonces is solved).
300 lines
9.8 KiB
Plaintext
300 lines
9.8 KiB
Plaintext
/**
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* X17 algorithm (X15 + sha512 + haval256)
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*/
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extern "C" {
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#include "sph/sph_blake.h"
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#include "sph/sph_bmw.h"
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#include "sph/sph_groestl.h"
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#include "sph/sph_skein.h"
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#include "sph/sph_jh.h"
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#include "sph/sph_keccak.h"
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#include "sph/sph_luffa.h"
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#include "sph/sph_cubehash.h"
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#include "sph/sph_shavite.h"
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#include "sph/sph_simd.h"
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#include "sph/sph_echo.h"
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#include "sph/sph_hamsi.h"
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#include "sph/sph_fugue.h"
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#include "sph/sph_shabal.h"
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#include "sph/sph_whirlpool.h"
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#include "sph/sph_sha2.h"
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#include "sph/sph_haval.h"
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}
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#include "miner.h"
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#include "cuda_helper.h"
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#include "x11/cuda_x11.h"
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static uint32_t *d_hash[MAX_GPUS];
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extern void x13_hamsi512_cpu_init(int thr_id, uint32_t threads);
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extern void x13_hamsi512_cpu_hash_64(int thr_id, uint32_t threads, uint32_t startNounce, uint32_t *d_nonceVector, uint32_t *d_hash, int order);
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extern void x13_fugue512_cpu_init(int thr_id, uint32_t threads);
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extern void x13_fugue512_cpu_hash_64(int thr_id, uint32_t threads, uint32_t startNounce, uint32_t *d_nonceVector, uint32_t *d_hash, int order);
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extern void x13_fugue512_cpu_free(int thr_id);
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extern void x14_shabal512_cpu_init(int thr_id, uint32_t threads);
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extern void x14_shabal512_cpu_hash_64(int thr_id, uint32_t threads, uint32_t startNounce, uint32_t *d_nonceVector, uint32_t *d_hash, int order);
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extern void x15_whirlpool_cpu_init(int thr_id, uint32_t threads, int flag);
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extern void x15_whirlpool_cpu_hash_64(int thr_id, uint32_t threads, uint32_t startNounce, uint32_t *d_nonceVector, uint32_t *d_hash, int order);
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extern void x15_whirlpool_cpu_free(int thr_id);
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extern void x17_sha512_cpu_init(int thr_id, uint32_t threads);
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extern void x17_sha512_cpu_hash_64(int thr_id, uint32_t threads, uint32_t startNounce, uint32_t *d_nonceVector, uint32_t *d_hash, int order);
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extern void x17_haval256_cpu_init(int thr_id, uint32_t threads);
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extern void x17_haval256_cpu_hash_64(int thr_id, uint32_t threads, uint32_t startNounce, uint32_t *d_nonceVector, uint32_t *d_hash, int order);
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// X17 CPU Hash (Validation)
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extern "C" void x17hash(void *output, const void *input)
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{
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unsigned char _ALIGN(64) hash[128];
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// x11 + hamsi12-fugue13-shabal14-whirlpool15-sha512-haval256
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sph_blake512_context ctx_blake;
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sph_bmw512_context ctx_bmw;
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sph_groestl512_context ctx_groestl;
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sph_jh512_context ctx_jh;
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sph_keccak512_context ctx_keccak;
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sph_skein512_context ctx_skein;
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sph_luffa512_context ctx_luffa;
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sph_cubehash512_context ctx_cubehash;
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sph_shavite512_context ctx_shavite;
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sph_simd512_context ctx_simd;
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sph_echo512_context ctx_echo;
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sph_hamsi512_context ctx_hamsi;
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sph_fugue512_context ctx_fugue;
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sph_shabal512_context ctx_shabal;
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sph_whirlpool_context ctx_whirlpool;
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sph_sha512_context ctx_sha512;
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sph_haval256_5_context ctx_haval;
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sph_blake512_init(&ctx_blake);
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sph_blake512(&ctx_blake, input, 80);
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sph_blake512_close(&ctx_blake, hash);
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sph_bmw512_init(&ctx_bmw);
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sph_bmw512(&ctx_bmw, (const void*) hash, 64);
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sph_bmw512_close(&ctx_bmw, hash);
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sph_groestl512_init(&ctx_groestl);
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sph_groestl512(&ctx_groestl, (const void*) hash, 64);
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sph_groestl512_close(&ctx_groestl, hash);
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sph_skein512_init(&ctx_skein);
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sph_skein512(&ctx_skein, (const void*) hash, 64);
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sph_skein512_close(&ctx_skein, hash);
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sph_jh512_init(&ctx_jh);
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sph_jh512(&ctx_jh, (const void*) hash, 64);
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sph_jh512_close(&ctx_jh, hash);
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sph_keccak512_init(&ctx_keccak);
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sph_keccak512(&ctx_keccak, (const void*) hash, 64);
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sph_keccak512_close(&ctx_keccak, hash);
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sph_luffa512_init(&ctx_luffa);
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sph_luffa512(&ctx_luffa, (const void*) hash, 64);
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sph_luffa512_close (&ctx_luffa, hash);
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sph_cubehash512_init(&ctx_cubehash);
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sph_cubehash512(&ctx_cubehash, (const void*) hash, 64);
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sph_cubehash512_close(&ctx_cubehash, hash);
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sph_shavite512_init(&ctx_shavite);
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sph_shavite512(&ctx_shavite, (const void*) hash, 64);
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sph_shavite512_close(&ctx_shavite, hash);
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sph_simd512_init(&ctx_simd);
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sph_simd512(&ctx_simd, (const void*) hash, 64);
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sph_simd512_close(&ctx_simd, hash);
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sph_echo512_init(&ctx_echo);
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sph_echo512(&ctx_echo, (const void*) hash, 64);
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sph_echo512_close(&ctx_echo, hash);
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sph_hamsi512_init(&ctx_hamsi);
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sph_hamsi512(&ctx_hamsi, (const void*) hash, 64);
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sph_hamsi512_close(&ctx_hamsi, hash);
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sph_fugue512_init(&ctx_fugue);
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sph_fugue512(&ctx_fugue, (const void*) hash, 64);
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sph_fugue512_close(&ctx_fugue, hash);
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sph_shabal512_init(&ctx_shabal);
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sph_shabal512(&ctx_shabal, (const void*) hash, 64);
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sph_shabal512_close(&ctx_shabal, hash);
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sph_whirlpool_init(&ctx_whirlpool);
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sph_whirlpool (&ctx_whirlpool, (const void*) hash, 64);
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sph_whirlpool_close(&ctx_whirlpool, hash);
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sph_sha512_init(&ctx_sha512);
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sph_sha512(&ctx_sha512,(const void*) hash, 64);
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sph_sha512_close(&ctx_sha512,(void*) hash);
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sph_haval256_5_init(&ctx_haval);
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sph_haval256_5(&ctx_haval,(const void*) hash, 64);
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sph_haval256_5_close(&ctx_haval,hash);
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memcpy(output, hash, 32);
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}
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static bool init[MAX_GPUS] = { 0 };
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extern "C" int scanhash_x17(int thr_id, struct work* work, uint32_t max_nonce, unsigned long *hashes_done)
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{
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uint32_t *pdata = work->data;
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uint32_t *ptarget = work->target;
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const uint32_t first_nonce = pdata[19];
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uint32_t throughput = cuda_default_throughput(thr_id, 1U << 19); // 19=256*256*8;
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//if (init[thr_id]) throughput = min(throughput, max_nonce - first_nonce);
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if (opt_benchmark)
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((uint32_t*)ptarget)[7] = 0x00ff;
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if (!init[thr_id])
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{
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cudaSetDevice(device_map[thr_id]);
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if (opt_cudaschedule == -1 && gpu_threads == 1) {
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cudaDeviceReset();
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// reduce cpu usage
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cudaSetDeviceFlags(cudaDeviceScheduleBlockingSync);
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}
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gpulog(LOG_INFO, thr_id, "Intensity set to %g, %u cuda threads", throughput2intensity(throughput), throughput);
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quark_blake512_cpu_init(thr_id, throughput);
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quark_groestl512_cpu_init(thr_id, throughput);
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quark_skein512_cpu_init(thr_id, throughput);
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quark_bmw512_cpu_init(thr_id, throughput);
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quark_keccak512_cpu_init(thr_id, throughput);
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quark_jh512_cpu_init(thr_id, throughput);
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x11_luffaCubehash512_cpu_init(thr_id, throughput);
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x11_shavite512_cpu_init(thr_id, throughput);
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x11_simd512_cpu_init(thr_id, throughput);
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x11_echo512_cpu_init(thr_id, throughput);
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x13_hamsi512_cpu_init(thr_id, throughput);
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x13_fugue512_cpu_init(thr_id, throughput);
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x14_shabal512_cpu_init(thr_id, throughput);
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x15_whirlpool_cpu_init(thr_id, throughput, 0);
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x17_sha512_cpu_init(thr_id, throughput);
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x17_haval256_cpu_init(thr_id, throughput);
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CUDA_CALL_OR_RET_X(cudaMalloc(&d_hash[thr_id], 16 * sizeof(uint32_t) * throughput), 0);
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cuda_check_cpu_init(thr_id, throughput);
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init[thr_id] = true;
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}
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uint32_t _ALIGN(64) endiandata[20];
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for (int k=0; k < 20; k++)
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be32enc(&endiandata[k], pdata[k]);
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quark_blake512_cpu_setBlock_80(thr_id, endiandata);
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cuda_check_cpu_setTarget(ptarget);
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int warn = 0;
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do {
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int order = 0;
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// Hash with CUDA
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quark_blake512_cpu_hash_80(thr_id, throughput, pdata[19], d_hash[thr_id]); order++;
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quark_bmw512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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quark_groestl512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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quark_skein512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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quark_jh512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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quark_keccak512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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x11_luffaCubehash512_cpu_hash_64(thr_id, throughput, d_hash[thr_id], order++);
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x11_shavite512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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x11_simd512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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x11_echo512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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x13_hamsi512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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x13_fugue512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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x14_shabal512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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x15_whirlpool_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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x17_sha512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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x17_haval256_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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*hashes_done = pdata[19] - first_nonce + throughput;
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uint32_t foundNonce = cuda_check_hash(thr_id, throughput, pdata[19], d_hash[thr_id]);
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if (foundNonce != UINT32_MAX)
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{
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const uint32_t Htarg = ptarget[7];
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uint32_t _ALIGN(64) vhash64[8];
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be32enc(&endiandata[19], foundNonce);
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x17hash(vhash64, endiandata);
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if (vhash64[7] <= Htarg && fulltest(vhash64, ptarget)) {
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int res = 1;
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uint32_t secNonce = cuda_check_hash_suppl(thr_id, throughput, pdata[19], d_hash[thr_id], 1);
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work_set_target_ratio(work, vhash64);
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if (secNonce != 0) {
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be32enc(&endiandata[19], secNonce);
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x17hash(vhash64, endiandata);
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if (bn_hash_target_ratio(vhash64, ptarget) > work->shareratio[0])
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work_set_target_ratio(work, vhash64);
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pdata[21] = secNonce;
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res++;
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}
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pdata[19] = foundNonce;
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return res;
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} else {
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// x11+ coins could do some random error, but not on retry
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if (!warn) {
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warn++; continue;
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} else {
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gpulog(LOG_WARNING, thr_id, "result for %08x does not validate on CPU!", foundNonce);
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warn = 0;
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}
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}
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}
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if ((uint64_t)throughput + pdata[19] >= max_nonce) {
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pdata[19] = max_nonce;
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break;
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}
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pdata[19] += throughput;
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} while (pdata[19] < max_nonce && !work_restart[thr_id].restart);
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*hashes_done = pdata[19] - first_nonce;
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return 0;
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}
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// cleanup
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extern "C" void free_x17(int thr_id)
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{
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if (!init[thr_id])
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return;
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cudaThreadSynchronize();
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cudaFree(d_hash[thr_id]);
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quark_blake512_cpu_free(thr_id);
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quark_groestl512_cpu_free(thr_id);
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x11_simd512_cpu_free(thr_id);
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x13_fugue512_cpu_free(thr_id);
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x15_whirlpool_cpu_free(thr_id);
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cuda_check_cpu_free(thr_id);
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cudaDeviceSynchronize();
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init[thr_id] = false;
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}
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