From d0316220ddd94ce6a161bca68311b816739d4d71 Mon Sep 17 00:00:00 2001 From: Tanguy Pruvot Date: Sun, 23 Nov 2014 21:16:27 +0100 Subject: [PATCH] simd512: restore full maxwell power (typo) --- x11/cuda_x11_simd512.cu | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/x11/cuda_x11_simd512.cu b/x11/cuda_x11_simd512.cu index fb63c15..1a9272b 100644 --- a/x11/cuda_x11_simd512.cu +++ b/x11/cuda_x11_simd512.cu @@ -673,10 +673,10 @@ void x11_simd512_cpu_hash_64(int thr_id, int threads, uint32_t startNounce, uint dim3 grid((threads + threadsperblock-1) / threadsperblock); dim3 grid8(((threads + threadsperblock - 1) / threadsperblock) * 8); - x11_simd512_gpu_expand_64 <<>> (threads, startNounce, (uint64_t*)d_hash, d_nonceVector, d_temp4[thr_id]); + if (device_sm[device_map[thr_id]] >= 500) { - x11_simd512_gpu_compress_64_maxwell <<< grid8, block >>> (threads, startNounce, (uint64_t*)d_hash, d_nonceVector, d_temp4[thr_id], d_state[thr_id]); + x11_simd512_gpu_compress_64_maxwell <<< grid, block >>> (threads, startNounce, (uint64_t*)d_hash, d_nonceVector, d_temp4[thr_id], d_state[thr_id]); } else { x11_simd512_gpu_compress1_64 <<< grid, block >>> (threads, startNounce, (uint64_t*)d_hash, d_nonceVector, d_temp4[thr_id], d_state[thr_id]); x11_simd512_gpu_compress2_64 <<< grid, block >>> (threads, startNounce, (uint64_t*)d_hash, d_nonceVector, d_temp4[thr_id], d_state[thr_id]);