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Tune reg. count for qubit (luffa) algos
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@ -57,7 +57,7 @@ nvcc_ARCH = -gencode=arch=compute_50,code=\"sm_50,compute_50\"
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#nvcc_ARCH += -gencode=arch=compute_30,code=\"sm_30,compute_30\"
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nvcc_FLAGS = $(nvcc_ARCH) -I . @CUDA_CFLAGS@
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nvcc_FLAGS += $(JANSSON_INCLUDES)
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nvcc_FLAGS += $(JANSSON_INCLUDES) --ptxas-options="-v"
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# we're now targeting all major compute architectures within one binary.
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.cu.o:
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@ -66,6 +66,9 @@ nvcc_FLAGS += $(JANSSON_INCLUDES)
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blake32.o: blake32.cu
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$(NVCC) $(nvcc_FLAGS) --maxrregcount=64 -o $@ -c $<
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qubit/qubit_luffa512.o: qubit/qubit_luffa512.cu
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$(NVCC) $(nvcc_FLAGS) --maxrregcount=80 -o $@ -c $<
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# Luffa and Echo are faster with 80 registers than 128
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x11/cuda_x11_luffa512.o: x11/cuda_x11_luffa512.cu
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$(NVCC) $(nvcc_FLAGS) --maxrregcount=80 -o $@ -c $<
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