mirror of
https://github.com/GOSTSec/ccminer
synced 2025-01-11 15:27:56 +00:00
x16: optimised echo512-64 kernel for maxwell+
which keep the SM 3.0 compat with x11 kernel
This commit is contained in:
Tanguy Pruvot
parent
27199e2a4d
commit
13e333d3e2
@ -78,6 +78,7 @@ ccminer_SOURCES = elist.h miner.h compat.h \
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x15/whirlpool.cu x15/cuda_x15_whirlpool_sm3.cu \
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x16r/x16r.cu x16r/x16s.cu x16r/cuda_x16_echo512.cu x16r/cuda_x16_fugue512.cu \
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x16r/cuda_x16_shabal512.cu x16r/cuda_x16_simd512_80.cu \
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x16r/cuda_x16_echo512_64.cu \
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x17/x17.cu x17/hmq17.cu x17/cuda_x17_haval256.cu x17/cuda_x17_sha512.cu \
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x11/phi.cu x11/cuda_streebog_maxwell.cu \
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x11/c11.cu x11/s3.cu x11/sib.cu x11/veltor.cu x11/cuda_streebog.cu
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@ -596,6 +596,9 @@
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<CudaCompile Include="x16r\cuda_x16_fugue512.cu" />
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<CudaCompile Include="x16r\cuda_x16_shabal512.cu" />
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<CudaCompile Include="x16r\cuda_x16_simd512_80.cu" />
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<CudaCompile Include="x16r\cuda_x16_echo512_64.cu">
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<CodeGeneration>compute_50,sm_50;compute_52,sm_52</CodeGeneration>
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</CudaCompile>
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<CudaCompile Include="x17\x17.cu" />
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<CudaCompile Include="x17\cuda_x17_haval256.cu">
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</CudaCompile>
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@ -985,6 +985,9 @@
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<CudaCompile Include="x16r\cuda_x16_echo512.cu">
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<Filter>Source Files\CUDA\x16r</Filter>
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</CudaCompile>
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<CudaCompile Include="x16r\cuda_x16_echo512_64.cu">
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<Filter>Source Files\CUDA\x16r</Filter>
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</CudaCompile>
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<CudaCompile Include="x16r\cuda_x16_fugue512.cu">
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<Filter>Source Files\CUDA\x16r</Filter>
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</CudaCompile>
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248
x16r/cuda_x16_echo512_64.cu
Normal file
248
x16r/cuda_x16_echo512_64.cu
Normal file
@ -0,0 +1,248 @@
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/**
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* Echo512-64 kernel for maxwell, based on alexis work
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*/
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#include <cuda_helper.h>
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#include <cuda_vector_uint2x4.h>
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#include <cuda_vectors.h>
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#define INTENSIVE_GMF
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#include "tribus/cuda_echo512_aes.cuh"
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#ifdef __INTELLISENSE__
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#define __byte_perm(x, y, b) x
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#define atomicExch(p,y) (*p) = y
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#endif
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__device__
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static void echo_round_alexis(const uint32_t sharedMemory[4][256], uint32_t *W, uint32_t &k0)
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{
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// Big Sub Words
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#pragma unroll 16
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for (int idx = 0; idx < 16; idx++)
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AES_2ROUND(sharedMemory,W[(idx<<2) + 0], W[(idx<<2) + 1], W[(idx<<2) + 2], W[(idx<<2) + 3], k0);
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// Shift Rows
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#pragma unroll 4
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for (int i = 0; i < 4; i++){
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uint32_t t[4];
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/// 1, 5, 9, 13
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t[0] = W[i+ 4];
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t[1] = W[i+ 8];
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t[2] = W[i+24];
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t[3] = W[i+60];
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W[i + 4] = W[i + 20];
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W[i + 8] = W[i + 40];
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W[i +24] = W[i + 56];
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W[i +60] = W[i + 44];
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W[i +20] = W[i +36];
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W[i +40] = t[1];
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W[i +56] = t[2];
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W[i +44] = W[i +28];
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W[i +28] = W[i +12];
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W[i +12] = t[3];
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W[i +36] = W[i +52];
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W[i +52] = t[0];
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}
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// Mix Columns
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#pragma unroll 4
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for (int i = 0; i < 4; i++){ // Schleife über je 2*uint32_t
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#pragma unroll 4
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for (int idx = 0; idx < 64; idx += 16){ // Schleife über die elemnte
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uint32_t a[4];
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a[0] = W[idx + i];
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a[1] = W[idx + i + 4];
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a[2] = W[idx + i + 8];
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a[3] = W[idx + i +12];
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uint32_t ab = a[0] ^ a[1];
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uint32_t bc = a[1] ^ a[2];
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uint32_t cd = a[2] ^ a[3];
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uint32_t t, t2, t3;
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t = (ab & 0x80808080);
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t2 = (bc & 0x80808080);
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t3 = (cd & 0x80808080);
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uint32_t abx = (t >> 7) * 27U ^ ((ab^t) << 1);
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uint32_t bcx = (t2 >> 7) * 27U ^ ((bc^t2) << 1);
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uint32_t cdx = (t3 >> 7) * 27U ^ ((cd^t3) << 1);
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W[idx + i] = bc ^ a[3] ^ abx;
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W[idx + i + 4] = a[0] ^ cd ^ bcx;
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W[idx + i + 8] = ab ^ a[3] ^ cdx;
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W[idx + i +12] = ab ^ a[2] ^ (abx ^ bcx ^ cdx);
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}
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}
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}
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__global__ __launch_bounds__(128, 5) /* will force 80 registers */
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static void x16_echo512_gpu_hash_64(uint32_t threads, uint32_t *g_hash)
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{
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__shared__ uint32_t sharedMemory[4][256];
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aes_gpu_init128(sharedMemory);
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const uint32_t thread = (blockDim.x * blockIdx.x + threadIdx.x);
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uint32_t k0;
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uint32_t h[16];
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uint32_t hash[16];
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if (thread < threads)
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{
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uint32_t *Hash = &g_hash[thread<<4];
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*(uint2x4*)&h[ 0] = __ldg4((uint2x4*)&Hash[ 0]);
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*(uint2x4*)&h[ 8] = __ldg4((uint2x4*)&Hash[ 8]);
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*(uint2x4*)&hash[ 0] = *(uint2x4*)&h[ 0];
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*(uint2x4*)&hash[ 8] = *(uint2x4*)&h[ 8];
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__syncthreads();
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const uint32_t P[48] = {
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0xe7e9f5f5, 0xf5e7e9f5, 0xb3b36b23, 0xb3dbe7af, 0xa4213d7e, 0xf5e7e9f5, 0xb3b36b23, 0xb3dbe7af,
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//8-12
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0x01425eb8, 0xf5e7e9f5, 0xb3b36b23, 0xb3dbe7af, 0x65978b09, 0xf5e7e9f5, 0xb3b36b23, 0xb3dbe7af,
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//21-25
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0x2cb6b661, 0x6b23b3b3, 0xcf93a7cf, 0x9d9d3751, 0x9ac2dea3, 0xf5e7e9f5, 0xb3b36b23, 0xb3dbe7af,
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//34-38
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0x579f9f33, 0xfbfbfbfb, 0xfbfbfbfb, 0xefefd3c7, 0xdbfde1dd, 0xf5e7e9f5, 0xb3b36b23, 0xb3dbe7af,
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0x34514d9e, 0xf5e7e9f5, 0xb3b36b23, 0xb3dbe7af, 0xb134347e, 0xea6f7e7e, 0xbd7731bd, 0x8a8a1968,
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0x14b8a457, 0xf5e7e9f5, 0xb3b36b23, 0xb3dbe7af, 0x265f4382, 0xf5e7e9f5, 0xb3b36b23, 0xb3dbe7af
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//58-61
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};
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k0 = 520;
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#pragma unroll 4
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for (uint32_t idx = 0; idx < 16; idx += 4) {
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AES_2ROUND(sharedMemory, h[idx + 0], h[idx + 1], h[idx + 2], h[idx + 3], k0);
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}
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k0 += 4;
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uint32_t W[64];
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#pragma unroll 4
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for (uint32_t i = 0; i < 4; i++)
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{
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uint32_t a = P[i];
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uint32_t b = P[i + 4];
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uint32_t c = h[i + 8];
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uint32_t d = P[i + 8];
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uint32_t ab = a ^ b;
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uint32_t bc = b ^ c;
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uint32_t cd = c ^ d;
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uint32_t t = (ab & 0x80808080);
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uint32_t t2 = (bc & 0x80808080);
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uint32_t t3 = (cd & 0x80808080);
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uint32_t abx = (t >> 7) * 27U ^ ((ab^t) << 1);
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uint32_t bcx = (t2 >> 7) * 27U ^ ((bc^t2) << 1);
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uint32_t cdx = (t3 >> 7) * 27U ^ ((cd^t3) << 1);
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W[i] = abx ^ bc ^ d;
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W[i + 4] = bcx ^ a ^ cd;
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W[i + 8] = cdx ^ ab ^ d;
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W[i +12] = abx ^ bcx ^ cdx ^ ab ^ c;
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a = P[i +12];
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b = h[i + 4];
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c = P[i +16];
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d = P[i +20];
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ab = a ^ b;
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bc = b ^ c;
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cd = c ^ d;
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t = (ab & 0x80808080);
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t2 = (bc & 0x80808080);
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t3 = (cd & 0x80808080);
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abx = (t >> 7) * 27U ^ ((ab^t) << 1);
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bcx = (t2 >> 7) * 27U ^ ((bc^t2) << 1);
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cdx = (t3 >> 7) * 27U ^ ((cd^t3) << 1);
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W[16 + i] = bc ^ d ^ abx;
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W[16 + i + 4] = a ^ cd ^ bcx;
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W[16 + i + 8] = d ^ ab ^ cdx;
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W[16 + i + 12] = c ^ ab ^ abx ^ bcx ^ cdx;
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a = h[i];
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b = P[24 + i + 0];
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c = P[24 + i + 4];
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d = P[24 + i + 8];
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ab = a ^ b;
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bc = b ^ c;
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cd = c ^ d;
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t = (ab & 0x80808080);
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t2 = (bc & 0x80808080);
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t3 = (cd & 0x80808080);
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abx = (t >> 7) * 27U ^ ((ab^t) << 1);
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bcx = (t2 >> 7) * 27U ^ ((bc^t2) << 1);
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cdx = (t3 >> 7) * 27U ^ ((cd^t3) << 1);
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W[32 + i] = bc ^ d ^ abx;
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W[32 + i + 4] = a ^ cd ^ bcx;
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W[32 + i + 8] = d ^ ab ^ cdx;
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W[32 + i + 12] = c ^ ab ^ abx ^ bcx ^ cdx;
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a = P[36 + i ];
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b = P[36 + i + 4];
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c = P[36 + i + 8];
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d = h[i + 12];
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ab = a ^ b;
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bc = b ^ c;
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cd = c ^ d;
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t = (ab & 0x80808080);
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t2 = (bc & 0x80808080);
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t3 = (cd & 0x80808080);
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abx = (t >> 7) * 27U ^ ((ab^t) << 1);
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bcx = (t2 >> 7) * 27U ^ ((bc^t2) << 1);
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cdx = (t3 >> 7) * 27U ^ ((cd^t3) << 1);
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W[48 + i] = bc ^ d ^ abx;
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W[48 + i + 4] = a ^ cd ^ bcx;
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W[48 + i + 8] = d ^ ab ^ cdx;
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W[48 + i + 12] = c ^ ab ^ abx ^ bcx ^ cdx;
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}
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for (int k = 1; k < 10; k++)
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echo_round_alexis(sharedMemory,W,k0);
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#pragma unroll 4
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for (int i = 0; i < 16; i += 4)
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{
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W[i] ^= W[32 + i] ^ 512;
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W[i + 1] ^= W[32 + i + 1];
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W[i + 2] ^= W[32 + i + 2];
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W[i + 3] ^= W[32 + i + 3];
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}
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*(uint2x4*)&Hash[ 0] = *(uint2x4*)&hash[ 0] ^ *(uint2x4*)&W[ 0];
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*(uint2x4*)&Hash[ 8] = *(uint2x4*)&hash[ 8] ^ *(uint2x4*)&W[ 8];
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}
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}
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__host__
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void x16_echo512_cpu_hash_64(int thr_id, uint32_t threads, uint32_t *d_hash){
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const uint32_t threadsperblock = 128;
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dim3 grid((threads + threadsperblock-1)/threadsperblock);
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dim3 block(threadsperblock);
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x16_echo512_gpu_hash_64<<<grid, block>>>(threads, d_hash);
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}
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@ -22,6 +22,10 @@ extern void x17_haval256_cpu_hash_64(int thr_id, uint32_t threads, uint32_t star
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void quark_blake512_cpu_hash_64(int thr_id, uint32_t threads, uint32_t startNonce, uint32_t *d_nonceVector, uint32_t *d_outputHash, int order);
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// ---- optimised but non compatible kernels
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void x16_echo512_cpu_hash_64(int thr_id, uint32_t threads, uint32_t *d_hash);
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// ---- 80 bytes kernels
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void quark_bmw512_cpu_setBlock_80(void *pdata);
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12
x16r/x16r.cu
12
x16r/x16r.cu
@ -227,6 +227,7 @@ void whirlpool_midstate(void *state, const void *input)
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}
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static bool init[MAX_GPUS] = { 0 };
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static bool use_compat_kernels[MAX_GPUS] = { 0 };
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//#define _DEBUG
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#define _DEBUG_PREFIX "x16r-"
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@ -257,6 +258,11 @@ extern "C" int scanhash_x16r(int thr_id, struct work* work, uint32_t max_nonce,
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}
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gpulog(LOG_INFO, thr_id, "Intensity set to %g, %u cuda threads", throughput2intensity(throughput), throughput);
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cuda_get_arch(thr_id);
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use_compat_kernels[thr_id] = (cuda_arch[dev_id] < 500);
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if (use_compat_kernels[thr_id])
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x11_echo512_cpu_init(thr_id, throughput);
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quark_blake512_cpu_init(thr_id, throughput);
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quark_bmw512_cpu_init(thr_id, throughput);
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quark_groestl512_cpu_init(thr_id, throughput);
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@ -267,7 +273,6 @@ extern "C" int scanhash_x16r(int thr_id, struct work* work, uint32_t max_nonce,
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x11_luffa512_cpu_init(thr_id, throughput); // 64
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x11_shavite512_cpu_init(thr_id, throughput);
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x11_simd512_cpu_init(thr_id, throughput); // 64
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x11_echo512_cpu_init(thr_id, throughput);
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x16_echo512_cuda_init(thr_id, throughput);
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x13_hamsi512_cpu_init(thr_id, throughput);
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x13_fugue512_cpu_init(thr_id, throughput);
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@ -484,7 +489,10 @@ extern "C" int scanhash_x16r(int thr_id, struct work* work, uint32_t max_nonce,
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TRACE("simd :");
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break;
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case ECHO:
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x11_echo512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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if (use_compat_kernels[thr_id])
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x11_echo512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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else
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x16_echo512_cpu_hash_64(thr_id, throughput, d_hash[thr_id]); order++;
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TRACE("echo :");
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break;
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case HAMSI:
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12
x16r/x16s.cu
12
x16r/x16s.cu
@ -229,6 +229,7 @@ void whirlpool_midstate(void *state, const void *input)
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#endif
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static bool init[MAX_GPUS] = { 0 };
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static bool use_compat_kernels[MAX_GPUS] = { 0 };
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//#define _DEBUG
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#define _DEBUG_PREFIX "x16s-"
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@ -255,6 +256,11 @@ extern "C" int scanhash_x16s(int thr_id, struct work* work, uint32_t max_nonce,
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}
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gpulog(LOG_INFO, thr_id, "Intensity set to %g, %u cuda threads", throughput2intensity(throughput), throughput);
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cuda_get_arch(thr_id);
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use_compat_kernels[thr_id] = (cuda_arch[dev_id] < 500);
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if (use_compat_kernels[thr_id])
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x11_echo512_cpu_init(thr_id, throughput);
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quark_blake512_cpu_init(thr_id, throughput);
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quark_bmw512_cpu_init(thr_id, throughput);
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quark_groestl512_cpu_init(thr_id, throughput);
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@ -265,7 +271,6 @@ extern "C" int scanhash_x16s(int thr_id, struct work* work, uint32_t max_nonce,
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x11_luffa512_cpu_init(thr_id, throughput); // 64
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x11_shavite512_cpu_init(thr_id, throughput);
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x11_simd512_cpu_init(thr_id, throughput); // 64
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x11_echo512_cpu_init(thr_id, throughput);
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x16_echo512_cuda_init(thr_id, throughput);
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x13_hamsi512_cpu_init(thr_id, throughput);
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x13_fugue512_cpu_init(thr_id, throughput);
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@ -482,7 +487,10 @@ extern "C" int scanhash_x16s(int thr_id, struct work* work, uint32_t max_nonce,
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TRACE("simd :");
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break;
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case ECHO:
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x11_echo512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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if (use_compat_kernels[thr_id])
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x11_echo512_cpu_hash_64(thr_id, throughput, pdata[19], NULL, d_hash[thr_id], order++);
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else
|
||||
x16_echo512_cpu_hash_64(thr_id, throughput, d_hash[thr_id]); order++;
|
||||
TRACE("echo :");
|
||||
break;
|
||||
case HAMSI:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user