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nvapi: fan level, for future use... maybe

2upstream
Tanguy Pruvot 9 years ago
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24436febd6
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036473347e
3 changed files with 214 additions and 31 deletions
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  1. 113
      compat/nvapi/nvapi_ccminer.h
  2. 87
      nvapi.cpp
  3. 43
      nvml.cpp

113
compat/nvapi/nvapi_ccminer.h
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@ -220,41 +220,89 @@ typedef struct {
NvU64 val2; // seen 7 and 3 NvU64 val2; // seen 7 and 3
NvU64 values[3]; // increment with time NvU64 values[3]; // increment with time
NvU32 pad[326]; // empty NvU32 pad[326]; // empty
} } NVAPI_GPU_PERF_STATUS; // 1360 bytes (1-0550)
NVAPI_GPU_PERF_STATUS; // 1360 bytes (1-0550)
#define NVAPI_GPU_PERF_STATUS_VER MAKE_NVAPI_VERSION(NVAPI_GPU_PERF_STATUS, 1) #define NVAPI_GPU_PERF_STATUS_VER MAKE_NVAPI_VERSION(NVAPI_GPU_PERF_STATUS, 1)
typedef struct {
NvU32 version;
NvU32 val1; // 4
NvU32 val2; // 2 or 0
NvU32 val3; // 2
NvU32 val4; // 3
NV_GPU_PERF_PSTATE_ID pStateId;
NvU32 val6; // 0 or 2
NvU32 val7; // 4
NvU32 val8; // 0
NvU32 memFreq1; // 405000.
NvU32 memFreq2; // 405000.
NvU32 memFreqMin;// 101250.
NvU32 memFreqMax;// 486000.
NvU32 zeros[3];
NvU32 gpuFreq1; // 696000. Unsure about those
NvU32 gpuFreq2; // 696000.
NvU32 gpuFreqMin;// 174000.
NvU32 gpuFreqMax;// 658000.
NvU32 pad[2697];
} NVAPI_GPU_PERF_CLOCKS; // 10868 bytes (2-2a74)
#define NVAPI_GPU_PERF_CLOCKS_VER MAKE_NVAPI_VERSION(NVAPI_GPU_PERF_CLOCKS, 2)
typedef struct {
NvU32 version;
NvU32 level;
NvU32 count;
NvU32 pad[339]; // (4-0558)
} NVAPI_COOLER_SETTINGS;
#define NVAPI_COOLER_SETTINGS_VER MAKE_NVAPI_VERSION(NVAPI_COOLER_SETTINGS, 4)
typedef struct {
NvU32 version;
NvU32 level; // 0 = auto ?
NvU32 count; // 1
NvU32 pad[38]; // (1-00a4)
} NVAPI_COOLER_LEVEL;
#define NVAPI_COOLER_LEVEL_VER MAKE_NVAPI_VERSION(NVAPI_COOLER_LEVEL, 1)
NvAPI_Status NvAPI_DLL_GetInterfaceVersionString(NvAPI_ShortString string); NvAPI_Status NvAPI_DLL_GetInterfaceVersionString(NvAPI_ShortString string);
NvAPI_Status NvAPI_DLL_PerfPoliciesGetInfo(NvPhysicalGpuHandle, NVAPI_GPU_PERF_INFO*); // 409D9841 1-004c NvAPI_Status NvAPI_DLL_PerfPoliciesGetInfo(NvPhysicalGpuHandle, NVAPI_GPU_PERF_INFO*); // 409D9841 1-004c
NvAPI_Status NvAPI_DLL_PerfPoliciesGetStatus(NvPhysicalGpuHandle, NVAPI_GPU_PERF_STATUS*); // 3D358A0C 1-0550 NvAPI_Status NvAPI_DLL_PerfPoliciesGetStatus(NvPhysicalGpuHandle, NVAPI_GPU_PERF_STATUS*); // 3D358A0C 1-0550
NvAPI_Status NvAPI_DLL_ClientPowerPoliciesGetInfo(NvPhysicalGpuHandle hPhysicalGpu, NVAPI_GPU_POWER_INFO*); NvAPI_Status NvAPI_DLL_ClientPowerPoliciesGetInfo(NvPhysicalGpuHandle, NVAPI_GPU_POWER_INFO*);
NvAPI_Status NvAPI_DLL_ClientPowerPoliciesGetStatus(NvPhysicalGpuHandle hPhysicalGpu, NVAPI_GPU_POWER_STATUS*); NvAPI_Status NvAPI_DLL_ClientPowerPoliciesGetStatus(NvPhysicalGpuHandle, NVAPI_GPU_POWER_STATUS*);
NvAPI_Status NvAPI_DLL_ClientPowerPoliciesSetStatus(NvPhysicalGpuHandle hPhysicalGpu, NVAPI_GPU_POWER_STATUS*); NvAPI_Status NvAPI_DLL_ClientPowerPoliciesSetStatus(NvPhysicalGpuHandle, NVAPI_GPU_POWER_STATUS*);
NvAPI_Status NvAPI_DLL_ClientPowerTopologyGetStatus(NvPhysicalGpuHandle hPhysicalGpu, NVAPI_GPU_POWER_TOPO*); // EDCF624E 1-0048 NvAPI_Status NvAPI_DLL_ClientPowerTopologyGetStatus(NvPhysicalGpuHandle, NVAPI_GPU_POWER_TOPO*); // EDCF624E 1-0048
NvAPI_Status NvAPI_DLL_ClientThermalPoliciesGetInfo(NvPhysicalGpuHandle hPhysicalGpu, NVAPI_GPU_THERMAL_INFO*); NvAPI_Status NvAPI_DLL_ClientThermalPoliciesGetInfo(NvPhysicalGpuHandle, NVAPI_GPU_THERMAL_INFO*);
NvAPI_Status NvAPI_DLL_ClientThermalPoliciesGetLimit(NvPhysicalGpuHandle hPhysicalGpu, NVAPI_GPU_THERMAL_LIMIT*); NvAPI_Status NvAPI_DLL_ClientThermalPoliciesGetLimit(NvPhysicalGpuHandle, NVAPI_GPU_THERMAL_LIMIT*);
NvAPI_Status NvAPI_DLL_ClientThermalPoliciesSetLimit(NvPhysicalGpuHandle hPhysicalGpu, NVAPI_GPU_THERMAL_LIMIT*); NvAPI_Status NvAPI_DLL_ClientThermalPoliciesSetLimit(NvPhysicalGpuHandle, NVAPI_GPU_THERMAL_LIMIT*);
// Pascal GTX only // Pascal GTX only
NvAPI_Status NvAPI_DLL_GetClockBoostRanges(NvPhysicalGpuHandle hPhysicalGpu, NVAPI_CLOCKS_RANGE*); NvAPI_Status NvAPI_DLL_GetClockBoostRanges(NvPhysicalGpuHandle, NVAPI_CLOCKS_RANGE*);
NvAPI_Status NvAPI_DLL_GetClockBoostMask(NvPhysicalGpuHandle hPhysicalGpu, NVAPI_CLOCK_MASKS*); // 0x507B4B59 NvAPI_Status NvAPI_DLL_GetClockBoostMask(NvPhysicalGpuHandle, NVAPI_CLOCK_MASKS*); // 0x507B4B59
NvAPI_Status NvAPI_DLL_GetClockBoostTable(NvPhysicalGpuHandle hPhysicalGpu, NVAPI_CLOCK_TABLE*); // 0x23F1B133 NvAPI_Status NvAPI_DLL_GetClockBoostTable(NvPhysicalGpuHandle, NVAPI_CLOCK_TABLE*); // 0x23F1B133
NvAPI_Status NvAPI_DLL_SetClockBoostTable(NvPhysicalGpuHandle hPhysicalGpu, NVAPI_CLOCK_TABLE*); // 0x0733E009 NvAPI_Status NvAPI_DLL_SetClockBoostTable(NvPhysicalGpuHandle, NVAPI_CLOCK_TABLE*); // 0x0733E009
NvAPI_Status NvAPI_DLL_GetVFPCurve(NvPhysicalGpuHandle hPhysicalGpu, NVAPI_VFP_CURVE*); // 0x21537AD4 NvAPI_Status NvAPI_DLL_GetVFPCurve(NvPhysicalGpuHandle, NVAPI_VFP_CURVE*); // 0x21537AD4
NvAPI_Status NvAPI_DLL_GetCurrentVoltage(NvPhysicalGpuHandle handle, NVAPI_VOLTAGE_STATUS* status); // 0x465F9BCF 1-004c NvAPI_Status NvAPI_DLL_GetCurrentVoltage(NvPhysicalGpuHandle, NVAPI_VOLTAGE_STATUS*); // 0x465F9BCF 1-004c
NvAPI_Status NvAPI_DLL_GetCoreVoltageBoostPercent(NvPhysicalGpuHandle handle, NVAPI_VOLTBOOST_PERCENT*); NvAPI_Status NvAPI_DLL_GetCoreVoltageBoostPercent(NvPhysicalGpuHandle, NVAPI_VOLTBOOST_PERCENT*);
NvAPI_Status NvAPI_DLL_SetCoreVoltageBoostPercent(NvPhysicalGpuHandle handle, NVAPI_VOLTBOOST_PERCENT*); NvAPI_Status NvAPI_DLL_SetCoreVoltageBoostPercent(NvPhysicalGpuHandle, NVAPI_VOLTBOOST_PERCENT*);
// Maxwell only // Maxwell only
NvAPI_Status NvAPI_DLL_GetVoltageDomainsStatus(NvPhysicalGpuHandle hPhysicalGpu, NVAPI_VOLT_STATUS*); // 0xC16C7E2C NvAPI_Status NvAPI_DLL_GetVoltageDomainsStatus(NvPhysicalGpuHandle, NVAPI_VOLT_STATUS*); // 0xC16C7E2C
NvAPI_Status NvAPI_DLL_GetVoltages(NvPhysicalGpuHandle handle, NVAPI_VOLTAGES_TABLE*); // 7D656244 1-40CC NvAPI_Status NvAPI_DLL_GetVoltages(NvPhysicalGpuHandle, NVAPI_VOLTAGES_TABLE*); // 0x7D656244 1-40CC
NvAPI_Status NvAPI_DLL_GetVoltageStep(NvPhysicalGpuHandle, NVAPI_VOLT_STATUS*); // 0x28766157 1-008C unsure of the name
NvAPI_Status NvAPI_DLL_GetCoolerSettings(NvPhysicalGpuHandle, uint32_t, NVAPI_COOLER_SETTINGS*); // 0xDA141340 4-0558
NvAPI_Status NvAPI_DLL_SetCoolerLevels(NvPhysicalGpuHandle, uint32_t, NVAPI_COOLER_LEVEL*); // 0x891FA0AE 1-00A4
NvAPI_Status NvAPI_DLL_RestoreCoolerSettings(NvPhysicalGpuHandle, NVAPI_COOLER_SETTINGS*, uint32_t);
NvAPI_Status NvAPI_DLL_GetSerialNumber(NvPhysicalGpuHandle, NvAPI_ShortString serial);
NvAPI_Status NvAPI_DLL_GetPerfClocks(NvPhysicalGpuHandle hPhysicalGpu, void* pFreqs); NvAPI_Status NvAPI_DLL_GetPerfClocks(NvPhysicalGpuHandle, uint32_t num, NVAPI_GPU_PERF_CLOCKS* pClocks); // 2-2A74
//NvAPI_Status NvAPI_DLL_SetPerfClocks(NvPhysicalGpuHandle, uint32_t num, NVAPI_GPU_PERF_CLOCKS* pClocks); // error
NvAPI_Status NvAPI_DLL_GetSerialNumber(NvPhysicalGpuHandle handle, NvAPI_ShortString serial); //invalid..
//NvAPI_Status NvAPI_DLL_GetPstateClientLimits(NvPhysicalGpuHandle, NV_GPU_PERF_PSTATE_ID, uint32_t* pLimits);
//NvAPI_Status NvAPI_DLL_SetPstateClientLimits(NvPhysicalGpuHandle, NV_GPU_PERF_PSTATE_ID, uint32_t* pLimits);
NvAPI_Status NvAPI_DLL_SetPstates20v1(NvPhysicalGpuHandle handle, NV_GPU_PERF_PSTATES20_INFO_V1 *pSet); NvAPI_Status NvAPI_DLL_SetPstates20v1(NvPhysicalGpuHandle handle, NV_GPU_PERF_PSTATES20_INFO_V1 *pSet);
NvAPI_Status NvAPI_DLL_SetPstates20v2(NvPhysicalGpuHandle handle, NV_GPU_PERF_PSTATES20_INFO_V2 *pSet); NvAPI_Status NvAPI_DLL_SetPstates20v2(NvPhysicalGpuHandle handle, NV_GPU_PERF_PSTATES20_INFO_V2 *pSet);
@ -294,6 +342,29 @@ typedef struct
} NV_I2C_INFO_EX; } NV_I2C_INFO_EX;
#define NV_I2C_INFO_EX_VER MAKE_NVAPI_VERSION(NV_I2C_INFO_EX,3) #define NV_I2C_INFO_EX_VER MAKE_NVAPI_VERSION(NV_I2C_INFO_EX,3)
/*
sample evga x64 call (struct of 0x40 bytes)
ReadEx
$ ==> 40 00 03 00 00 00 00 00 00 40 00 00 00 00 00 00
$+10 58 F9 2B 00 00 00 00 00 01 00 00 00 00 00 00 00
$+20 C0 F9 2B 00 00 00 00 00 02 00 00 00 FF FF 00 00
$+30 00 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00
$ ==> 40 00 03 00 00 00 00 00 00 10 00 00 00 00 00 00
$+10 68 F9 2B 00 00 00 00 00 01 00 00 00 00 00 00 00
$+20 C0 F9 2B 00 00 00 00 00 01 00 00 00 FF FF 00 00
$+30 00 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00
00000000002BF968 > 75 83 CF 3F 01 00 00 00
00000000002BF9C0 > 0
WriteEx
$ ==> 40 00 03 00 00 00 00 00 00 8C 00 00 00 00 00 00
$+10 30 F9 2B 00 00 00 00 00 01 00 00 00 00 00 00 00
$+20 38 F9 2B 00 00 00 00 00 02 00 00 00 FF FF 00 00
$+30 00 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00
00000000002BF930 > D1 00 00 00 00 00 00 00
00000000002BF938 > 38 00 00 00 00 00 00 00
*/
NvAPI_Status NvAPI_DLL_I2CReadEx(NvPhysicalGpuHandle, NV_I2C_INFO_EX*, NvU32*); NvAPI_Status NvAPI_DLL_I2CReadEx(NvPhysicalGpuHandle, NV_I2C_INFO_EX*, NvU32*);
NvAPI_Status NvAPI_DLL_I2CWriteEx(NvPhysicalGpuHandle, NV_I2C_INFO_EX*, NvU32*); NvAPI_Status NvAPI_DLL_I2CWriteEx(NvPhysicalGpuHandle, NV_I2C_INFO_EX*, NvU32*);

87
nvapi.cpp
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@ -211,7 +211,7 @@ NvAPI_Status NvAPI_DLL_GetCurrentVoltage(NvPhysicalGpuHandle handle, NVAPI_VOLTA
return (*pointer)(handle, status); return (*pointer)(handle, status);
} }
#define NVAPI_ID_VOLT_STATUS_GET 0xC16C7E2C #define NVAPI_ID_VOLT_STATUS_GET 0xC16C7E2C // Maxwell
NvAPI_Status NvAPI_DLL_GetVoltageDomainsStatus(NvPhysicalGpuHandle handle, NVAPI_VOLT_STATUS* data) { NvAPI_Status NvAPI_DLL_GetVoltageDomainsStatus(NvPhysicalGpuHandle handle, NVAPI_VOLT_STATUS* data) {
static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, NVAPI_VOLT_STATUS*) = NULL; static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, NVAPI_VOLT_STATUS*) = NULL;
if(!nvapi_dll_loaded) return NVAPI_API_NOT_INITIALIZED; if(!nvapi_dll_loaded) return NVAPI_API_NOT_INITIALIZED;
@ -222,6 +222,17 @@ NvAPI_Status NvAPI_DLL_GetVoltageDomainsStatus(NvPhysicalGpuHandle handle, NVAPI
return (*pointer)(handle, data); return (*pointer)(handle, data);
} }
#define NVAPI_ID_VOLTAGE 0x28766157 // Maxwell 1-008c Real func name is unknown
NvAPI_Status NvAPI_DLL_GetVoltageStep(NvPhysicalGpuHandle handle, NVAPI_VOLT_STATUS* data) {
static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, NVAPI_VOLT_STATUS*) = NULL;
if(!nvapi_dll_loaded) return NVAPI_API_NOT_INITIALIZED;
if(!pointer) {
pointer = (NvAPI_Status (*)(NvPhysicalGpuHandle, NVAPI_VOLT_STATUS*))nvidia_handle->query(NVAPI_ID_VOLTAGE);
}
if(!pointer) return NVAPI_NO_IMPLEMENTATION;
return (*pointer)(handle, data);
}
#define NVAPI_ID_CLK_RANGE_GET 0x64B43A6A // Pascal #define NVAPI_ID_CLK_RANGE_GET 0x64B43A6A // Pascal
NvAPI_Status NvAPI_DLL_GetClockBoostRanges(NvPhysicalGpuHandle handle, NVAPI_CLOCKS_RANGE* range) { NvAPI_Status NvAPI_DLL_GetClockBoostRanges(NvPhysicalGpuHandle handle, NVAPI_CLOCKS_RANGE* range) {
static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, NVAPI_CLOCKS_RANGE*) = NULL; static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, NVAPI_CLOCKS_RANGE*) = NULL;
@ -302,14 +313,47 @@ NvAPI_Status NvAPI_DLL_SetCoreVoltageBoostPercent(NvPhysicalGpuHandle handle, NV
} }
#define NVAPI_ID_PERFCLOCKS_GET 0x1EA54A3B #define NVAPI_ID_PERFCLOCKS_GET 0x1EA54A3B
NvAPI_Status NvAPI_DLL_GetPerfClocks(NvPhysicalGpuHandle handle, void* pFreqs){ NvAPI_Status NvAPI_DLL_GetPerfClocks(NvPhysicalGpuHandle handle, uint32_t num, NVAPI_GPU_PERF_CLOCKS* pClocks) {
static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, void*) = NULL; static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, uint32_t, NVAPI_GPU_PERF_CLOCKS*) = NULL;
if(!nvapi_dll_loaded) return NVAPI_API_NOT_INITIALIZED;
if(!pointer) {
pointer = (NvAPI_Status (*)(NvPhysicalGpuHandle, uint32_t, NVAPI_GPU_PERF_CLOCKS*))nvidia_handle->query(NVAPI_ID_PERFCLOCKS_GET);
}
if(!pointer) return NVAPI_NO_IMPLEMENTATION;
return (*pointer)(handle, num, pClocks);
}
#define NVAPI_ID_PERFCLOCKS_SET 0x07BCF4AC // error
NvAPI_Status NvAPI_DLL_SetPerfClocks(NvPhysicalGpuHandle handle, uint32_t num, NVAPI_GPU_PERF_CLOCKS* pClocks) {
static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, uint32_t, NVAPI_GPU_PERF_CLOCKS*) = NULL;
if(!nvapi_dll_loaded) return NVAPI_API_NOT_INITIALIZED;
if(!pointer) {
pointer = (NvAPI_Status (*)(NvPhysicalGpuHandle, uint32_t, NVAPI_GPU_PERF_CLOCKS*))nvidia_handle->query(NVAPI_ID_PERFCLOCKS_SET);
}
if(!pointer) return NVAPI_NO_IMPLEMENTATION;
return (*pointer)(handle, num, pClocks);
}
#define NVAPI_ID_PSTATELIMITS_GET 0x88C82104 // wrong prototype or missing struct data ?
NvAPI_Status NvAPI_DLL_GetPstateClientLimits(NvPhysicalGpuHandle handle, NV_GPU_PERF_PSTATE_ID pst, uint32_t* pLimits) {
static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, NV_GPU_PERF_PSTATE_ID, uint32_t*) = NULL;
if(!nvapi_dll_loaded) return NVAPI_API_NOT_INITIALIZED;
if(!pointer) {
pointer = (NvAPI_Status (*)(NvPhysicalGpuHandle, NV_GPU_PERF_PSTATE_ID, uint32_t*))nvidia_handle->query(NVAPI_ID_PSTATELIMITS_GET);
}
if(!pointer) return NVAPI_NO_IMPLEMENTATION;
return (*pointer)(handle, pst, pLimits);
}
#define NVAPI_ID_PSTATELIMITS_SET 0xFDFC7D49 // wrong prototype or missing struct data ?
NvAPI_Status NvAPI_DLL_SetPstateClientLimits(NvPhysicalGpuHandle handle, NV_GPU_PERF_PSTATE_ID pst, uint32_t* pLimits) {
static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, NV_GPU_PERF_PSTATE_ID, uint32_t*) = NULL;
if(!nvapi_dll_loaded) return NVAPI_API_NOT_INITIALIZED; if(!nvapi_dll_loaded) return NVAPI_API_NOT_INITIALIZED;
if(!pointer) { if(!pointer) {
pointer = (NvAPI_Status (*)(NvPhysicalGpuHandle, void*))nvidia_handle->query(NVAPI_ID_PERFCLOCKS_GET); pointer = (NvAPI_Status (*)(NvPhysicalGpuHandle, NV_GPU_PERF_PSTATE_ID, uint32_t*))nvidia_handle->query(NVAPI_ID_PSTATELIMITS_SET);
} }
if(!pointer) return NVAPI_NO_IMPLEMENTATION; if(!pointer) return NVAPI_NO_IMPLEMENTATION;
return (*pointer)(handle, pFreqs); return (*pointer)(handle, pst, pLimits);
} }
#define NVAPI_ID_PSTATE20_SET 0x0F4DAE6B #define NVAPI_ID_PSTATE20_SET 0x0F4DAE6B
@ -347,6 +391,39 @@ NvAPI_Status NvAPI_DLL_GetVoltages(NvPhysicalGpuHandle handle, NVAPI_VOLTAGES_TA
return (*pointer)(handle, pInfo); return (*pointer)(handle, pInfo);
} }
#define NVAPI_ID_COOLERSETTINGS 0xDA141340 // 4-0558
NvAPI_Status NvAPI_DLL_GetCoolerSettings(NvPhysicalGpuHandle handle, uint32_t id, NVAPI_COOLER_SETTINGS* pSettings) {
static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, uint32_t, NVAPI_COOLER_SETTINGS*) = NULL;
if(!nvapi_dll_loaded) return NVAPI_API_NOT_INITIALIZED;
if(!pointer) {
pointer = (NvAPI_Status (*)(NvPhysicalGpuHandle, uint32_t, NVAPI_COOLER_SETTINGS*))nvidia_handle->query(NVAPI_ID_COOLERSETTINGS);
}
if(!pointer) return NVAPI_NO_IMPLEMENTATION;
return (*pointer)(handle, id, pSettings);
}
#define NVAPI_ID_COOLER_SETLEVELS 0x891FA0AE // 1-00A4
NvAPI_Status NvAPI_DLL_SetCoolerLevels(NvPhysicalGpuHandle handle, uint32_t id, NVAPI_COOLER_LEVEL* pLevel) {
static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, uint32_t, NVAPI_COOLER_LEVEL*) = NULL;
if(!nvapi_dll_loaded) return NVAPI_API_NOT_INITIALIZED;
if(!pointer) {
pointer = (NvAPI_Status (*)(NvPhysicalGpuHandle, uint32_t, NVAPI_COOLER_LEVEL*))nvidia_handle->query(NVAPI_ID_COOLER_SETLEVELS);
}
if(!pointer) return NVAPI_NO_IMPLEMENTATION;
return (*pointer)(handle, id, pLevel);
}
#define NVAPI_ID_COOLER_RESTORE 0x8F6ED0FB
NvAPI_Status NvAPI_DLL_RestoreCoolerSettings(NvPhysicalGpuHandle handle, NVAPI_COOLER_SETTINGS* pSettings, uint32_t id) {
static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, NVAPI_COOLER_SETTINGS*, uint32_t) = NULL;
if(!nvapi_dll_loaded) return NVAPI_API_NOT_INITIALIZED;
if(!pointer) {
pointer = (NvAPI_Status (*)(NvPhysicalGpuHandle, NVAPI_COOLER_SETTINGS*, uint32_t))nvidia_handle->query(NVAPI_ID_COOLER_RESTORE);
}
if(!pointer) return NVAPI_NO_IMPLEMENTATION;
return (*pointer)(handle, pSettings, id);
}
#define NVAPI_ID_I2CREADEX 0x4D7B0709 // 3-002c #define NVAPI_ID_I2CREADEX 0x4D7B0709 // 3-002c
NvAPI_Status NvAPI_DLL_I2CReadEx(NvPhysicalGpuHandle handle, NV_I2C_INFO_EX *i2c, NvU32 *exData) { NvAPI_Status NvAPI_DLL_I2CReadEx(NvPhysicalGpuHandle handle, NV_I2C_INFO_EX *i2c, NvU32 *exData) {
static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, NV_I2C_INFO_EX*, NvU32*) = NULL; static NvAPI_Status (*pointer)(NvPhysicalGpuHandle, NV_I2C_INFO_EX*, NvU32*) = NULL;

43
nvml.cpp
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@ -1031,7 +1031,9 @@ int nvapi_pstateinfo(unsigned int devNum)
uint32_t* buf = (uint32_t*) calloc(1, 0x8000); uint32_t* buf = (uint32_t*) calloc(1, 0x8000);
for (int i=8; i < 0x8000 && buf; i+=4) { for (int i=8; i < 0x8000 && buf; i+=4) {
buf[0] = 0x10000 + i; buf[0] = 0x10000 + i;
if ((ret = NvAPI_DLL_GetXXX(phys[devNum], buf)) != NVAPI_INCOMPATIBLE_STRUCT_VERSION) { NV_GPU_PERF_PSTATE_ID pst = NVAPI_GPU_PERF_PSTATE_P0;
ret = NvAPI_DLL_GetPstateClientLimits(phys[devNum], pst, buf);
if (ret != NVAPI_INCOMPATIBLE_STRUCT_VERSION) {
NvAPI_ShortString string; NvAPI_ShortString string;
NvAPI_GetErrorMessage(ret, string); NvAPI_GetErrorMessage(ret, string);
applog(LOG_BLUE, "struct size is %06x : %s", buf[0], string); applog(LOG_BLUE, "struct size is %06x : %s", buf[0], string);
@ -1111,6 +1113,19 @@ int nvapi_pstateinfo(unsigned int devNum)
(double) freqs->domain[NVAPI_GPU_PUBLIC_CLOCK_MEMORY].frequency / 1000, (double) freqs->domain[NVAPI_GPU_PUBLIC_CLOCK_MEMORY].frequency / 1000,
(double) freqs->domain[NVAPI_GPU_PUBLIC_CLOCK_GRAPHICS].frequency / 1000); (double) freqs->domain[NVAPI_GPU_PUBLIC_CLOCK_GRAPHICS].frequency / 1000);
// Other clock values ??
NVAPI_GPU_PERF_CLOCKS *pcl;
NV_INIT_STRUCT_ALLOC(NVAPI_GPU_PERF_CLOCKS, pcl);
int numClock=0; ret = NVAPI_OK;
while (ret == NVAPI_OK) {
if ((ret = NvAPI_DLL_GetPerfClocks(phys[devNum], numClock, pcl)) == NVAPI_OK) {
applog(LOG_RAW, " C%d: MEM %4.0f MHz GPU %6.1f MHz [%5.1f/%6.1f]", numClock,
(double) pcl->memFreq1/1000, (double) pcl->gpuFreq1/1000, (double) pcl->gpuFreqMin/1000, (double) pcl->gpuFreqMax/1000);
// ret = NvAPI_DLL_SetPerfClocks(phys[devNum], numClock, pcl); // error
}
numClock++;
}
// Pascal only // Pascal only
NVAPI_VOLTBOOST_PERCENT *pvb; NVAPI_VOLTBOOST_PERCENT *pvb;
NV_INIT_STRUCT_ON(NVAPI_VOLTBOOST_PERCENT, pvb, mem); NV_INIT_STRUCT_ON(NVAPI_VOLTBOOST_PERCENT, pvb, mem);
@ -1125,11 +1140,14 @@ int nvapi_pstateinfo(unsigned int devNum)
free(pvdom); free(pvdom);
} else { } else {
// Maxwell 9xx // Maxwell 9xx
NVAPI_VOLT_STATUS *mvdom; NVAPI_VOLT_STATUS *mvdom, *mvstep;
NV_INIT_STRUCT_ALLOC(NVAPI_VOLT_STATUS, mvdom); NV_INIT_STRUCT_ALLOC(NVAPI_VOLT_STATUS, mvdom);
if (mvdom && (ret = NvAPI_DLL_GetVoltageDomainsStatus(phys[devNum], mvdom)) == NVAPI_OK) { if (mvdom && (ret = NvAPI_DLL_GetVoltageDomainsStatus(phys[devNum], mvdom)) == NVAPI_OK) {
if (mvdom->value_uV) NV_INIT_STRUCT_ALLOC(NVAPI_VOLT_STATUS, mvstep);
applog(LOG_RAW, " GPU Voltage is %u mV", mvdom->value_uV/1000); NvAPI_DLL_GetVoltageStep(phys[devNum], mvstep);
if (mvdom->value_uV) applog(LOG_RAW, " GPU Voltage is %.1f mV with %.3f mV resolution",
(double) mvdom->value_uV/1000, (double) mvstep->value_uV/1000);
free(mvstep);
} }
free(mvdom); free(mvdom);
} }
@ -1137,6 +1155,23 @@ int nvapi_pstateinfo(unsigned int devNum)
uint32_t plim = nvapi_get_plimit(devNum); uint32_t plim = nvapi_get_plimit(devNum);
applog(LOG_RAW, " Power limit is set to %u%%", plim); applog(LOG_RAW, " Power limit is set to %u%%", plim);
NVAPI_COOLER_SETTINGS *cooler;
NV_INIT_STRUCT_ON(NVAPI_COOLER_SETTINGS, cooler, mem);
ret = NvAPI_DLL_GetCoolerSettings(phys[devNum], 7, cooler);
if (ret == NVAPI_OK) {
applog(LOG_RAW, " Fan level is set to %u%%", cooler->level);
#if 0
NVAPI_COOLER_LEVEL *fan;
NV_INIT_STRUCT_ALLOC(NVAPI_COOLER_LEVEL, fan);
fan->level = 100;
fan->count = 1;
ret = NvAPI_DLL_SetCoolerLevels(phys[devNum], 7, fan);
free(fan);
sleep(10);
ret = NvAPI_DLL_RestoreCoolerSettings(phys[devNum], cooler, 7);
#endif
}
NV_GPU_THERMAL_SETTINGS *tset; NV_GPU_THERMAL_SETTINGS *tset;
NV_INIT_STRUCT_ON(NV_GPU_THERMAL_SETTINGS, tset, mem); NV_INIT_STRUCT_ON(NV_GPU_THERMAL_SETTINGS, tset, mem);

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