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#include "cryptonight.h"
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extern char *device_config[MAX_GPUS]; // -l 32x16
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static __thread uint32_t cn_blocks;
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static __thread uint32_t cn_threads;
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// used for gpu intensity on algo init
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static __thread bool gpu_init_shown = false;
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#define gpulog_init(p,thr,fmt, ...) if (!gpu_init_shown) \
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gpulog(p, thr, fmt, ##__VA_ARGS__)
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static uint64_t *d_long_state[MAX_GPUS];
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static uint32_t *d_ctx_state[MAX_GPUS];
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static uint32_t *d_ctx_key1[MAX_GPUS];
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static uint32_t *d_ctx_key2[MAX_GPUS];
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static uint32_t *d_ctx_text[MAX_GPUS];
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static uint64_t *d_ctx_tweak[MAX_GPUS];
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static uint32_t *d_ctx_a[MAX_GPUS];
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static uint32_t *d_ctx_b[MAX_GPUS];
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static bool init[MAX_GPUS] = { 0 };
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extern "C" int scanhash_cryptonight(int thr_id, struct work* work, uint32_t max_nonce, unsigned long *hashes_done, int variant)
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{
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int res = 0;
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uint32_t throughput = 0;
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uint32_t *ptarget = work->target;
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uint8_t *pdata = (uint8_t*) work->data;
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uint32_t *nonceptr = (uint32_t*) (&pdata[39]);
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const uint32_t first_nonce = *nonceptr;
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uint32_t nonce = first_nonce;
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int dev_id = device_map[thr_id];
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if(opt_benchmark) {
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ptarget[7] = 0x00ff;
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}
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if(!init[thr_id])
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{
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int mem = cuda_available_memory(thr_id);
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int mul = device_sm[dev_id] >= 300 ? 4 : 1; // see cryptonight-core.cu
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cn_threads = device_sm[dev_id] >= 600 ? 16 : 8; // real TPB is x4 on SM3+
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cn_blocks = device_mpcount[dev_id] * 4;
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if (cn_blocks*cn_threads*2.2 > mem) cn_blocks = device_mpcount[dev_id] * 2;
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if (!opt_quiet)
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gpulog_init(LOG_INFO, thr_id, "%s, %d MB available, %hd SMX", device_name[dev_id],
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mem, device_mpcount[dev_id]);
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if (!device_config[thr_id] && strcmp(device_name[dev_id], "TITAN V") == 0) {
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device_config[thr_id] = strdup("80x24");
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}
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if (device_config[thr_id]) {
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int res = sscanf(device_config[thr_id], "%ux%u", &cn_blocks, &cn_threads);
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throughput = cuda_default_throughput(thr_id, cn_blocks*cn_threads);
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gpulog_init(LOG_INFO, thr_id, "Using %ux%u(x%d) kernel launch config, %u threads",
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cn_blocks, cn_threads, mul, throughput);
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} else {
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throughput = cuda_default_throughput(thr_id, cn_blocks*cn_threads);
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if (throughput != cn_blocks*cn_threads && cn_threads) {
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cn_blocks = throughput / cn_threads;
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throughput = cn_threads * cn_blocks;
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}
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gpulog_init(LOG_INFO, thr_id, "%u threads (%g) with %u blocks",// of %ux%d",
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throughput, throughput2intensity(throughput), cn_blocks);//, cn_threads, mul);
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}
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if(sizeof(size_t) == 4 && throughput > UINT32_MAX / MEMORY) {
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gpulog(LOG_ERR, thr_id, "THE 32bit VERSION CAN'T ALLOCATE MORE THAN 4GB OF MEMORY!");
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gpulog(LOG_ERR, thr_id, "PLEASE REDUCE THE NUMBER OF THREADS OR BLOCKS");
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exit(1);
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}
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cudaSetDevice(dev_id);
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if (opt_cudaschedule == -1 && gpu_threads == 1) {
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cudaDeviceReset();
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cudaSetDeviceFlags(cudaDeviceScheduleBlockingSync);
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cudaDeviceSetCacheConfig(cudaFuncCachePreferL1);
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CUDA_LOG_ERROR();
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}
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const size_t alloc = MEMORY * throughput;
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cryptonight_extra_init(thr_id);
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cudaMalloc(&d_long_state[thr_id], alloc);
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exit_if_cudaerror(thr_id, __FUNCTION__, __LINE__);
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cudaMalloc(&d_ctx_state[thr_id], 50 * sizeof(uint32_t) * throughput);
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exit_if_cudaerror(thr_id, __FUNCTION__, __LINE__);
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cudaMalloc(&d_ctx_key1[thr_id], 40 * sizeof(uint32_t) * throughput);
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exit_if_cudaerror(thr_id, __FUNCTION__, __LINE__);
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cudaMalloc(&d_ctx_key2[thr_id], 40 * sizeof(uint32_t) * throughput);
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exit_if_cudaerror(thr_id, __FUNCTION__, __LINE__);
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cudaMalloc(&d_ctx_text[thr_id], 32 * sizeof(uint32_t) * throughput);
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exit_if_cudaerror(thr_id, __FUNCTION__, __LINE__);
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cudaMalloc(&d_ctx_a[thr_id], 4 * sizeof(uint32_t) * throughput);
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exit_if_cudaerror(thr_id, __FUNCTION__, __LINE__);
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cudaMalloc(&d_ctx_b[thr_id], 4 * sizeof(uint32_t) * throughput);
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exit_if_cudaerror(thr_id, __FUNCTION__, __LINE__);
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cudaMalloc(&d_ctx_tweak[thr_id], sizeof(uint64_t) * throughput);
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exit_if_cudaerror(thr_id, __FILE__, __LINE__);
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gpu_init_shown = true;
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init[thr_id] = true;
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}
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throughput = cn_blocks*cn_threads;
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do
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{
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const uint32_t Htarg = ptarget[7];
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uint32_t resNonces[2] = { UINT32_MAX, UINT32_MAX };
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cryptonight_extra_setData(thr_id, pdata, ptarget);
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cryptonight_extra_prepare(thr_id, throughput, nonce, d_ctx_state[thr_id], d_ctx_a[thr_id], d_ctx_b[thr_id], d_ctx_key1[thr_id], d_ctx_key2[thr_id], variant, d_ctx_tweak[thr_id]);
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cryptonight_core_cuda(thr_id, cn_blocks, cn_threads, d_long_state[thr_id], d_ctx_state[thr_id], d_ctx_a[thr_id], d_ctx_b[thr_id], d_ctx_key1[thr_id], d_ctx_key2[thr_id], variant, d_ctx_tweak[thr_id]);
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cryptonight_extra_final(thr_id, throughput, nonce, resNonces, d_ctx_state[thr_id]);
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*hashes_done = nonce - first_nonce + throughput;
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if(resNonces[0] != UINT32_MAX)
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{
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uint32_t vhash[8];
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uint32_t tempdata[19];
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uint32_t *tempnonceptr = (uint32_t*)(((char*)tempdata) + 39);
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memcpy(tempdata, pdata, 76);
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*tempnonceptr = resNonces[0];
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const int rc = cryptonight_hash_variant(vhash, tempdata, 76, variant);
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if(rc && (vhash[7] <= Htarg) && fulltest(vhash, ptarget))
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{
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res = 1;
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work->nonces[0] = resNonces[0];
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work_set_target_ratio(work, vhash);
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// second nonce
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if(resNonces[1] != UINT32_MAX)
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{
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*tempnonceptr = resNonces[1];
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const int rc = cryptonight_hash_variant(vhash, tempdata, 76, variant);
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if(rc && (vhash[7] <= Htarg) && fulltest(vhash, ptarget)) {
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res++;
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work->nonces[1] = resNonces[1];
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} else {
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gpu_increment_reject(thr_id);
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}
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}
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goto done;
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} else if (vhash[7] > Htarg) {
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gpu_increment_reject(thr_id);
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if (!opt_quiet)
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gpulog(LOG_WARNING, thr_id, "result for nonce %08x does not validate on CPU!", resNonces[0]);
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}
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}
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if ((uint64_t) throughput + nonce >= max_nonce - 127) {
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nonce = max_nonce;
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break;
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}
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nonce += throughput;
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gpulog(LOG_DEBUG, thr_id, "nonce %08x", nonce);
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} while (!work_restart[thr_id].restart && max_nonce > (uint64_t)throughput + nonce);
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done:
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gpulog(LOG_DEBUG, thr_id, "nonce %08x exit", nonce);
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work->valid_nonces = res;
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*nonceptr = nonce;
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return res;
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}
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void free_cryptonight(int thr_id)
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{
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if (!init[thr_id])
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return;
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cudaFree(d_long_state[thr_id]);
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cudaFree(d_ctx_state[thr_id]);
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cudaFree(d_ctx_key1[thr_id]);
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cudaFree(d_ctx_key2[thr_id]);
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cudaFree(d_ctx_text[thr_id]);
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cudaFree(d_ctx_tweak[thr_id]);
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cudaFree(d_ctx_a[thr_id]);
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cudaFree(d_ctx_b[thr_id]);
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cryptonight_extra_free(thr_id);
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cudaDeviceSynchronize();
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init[thr_id] = false;
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}
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