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266 lines
10 KiB
266 lines
10 KiB
/* |
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* A trivial little dlopen()-based wrapper library for the |
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* NVIDIA NVML library, to allow runtime discovery of NVML on an |
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* arbitrary system. This is all very hackish and simple-minded, but |
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* it serves my immediate needs in the short term until NVIDIA provides |
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* a static NVML wrapper library themselves, hopefully in |
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* CUDA 6.5 or maybe sometime shortly after. |
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* |
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* This trivial code is made available under the "new" 3-clause BSD license, |
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* and/or any of the GPL licenses you prefer. |
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* Feel free to use the code and modify as you see fit. |
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* |
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* John E. Stone - john.stone@gmail.com |
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* |
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*/ |
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#ifdef USE_WRAPNVML |
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#include "miner.h" |
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void *monitor_thread(void *userdata); |
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typedef void * nvmlDevice_t; |
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#define NVML_DEVICE_PCI_BUS_ID_BUFFER_SIZE 16 |
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/* our own version of the PCI info struct */ |
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typedef struct { |
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char bus_id_str[NVML_DEVICE_PCI_BUS_ID_BUFFER_SIZE]; |
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unsigned int domain; |
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unsigned int bus; |
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unsigned int device; |
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unsigned int pci_device_id; /* combined device and vendor id */ |
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unsigned int pci_subsystem_id; |
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unsigned int res0; /* NVML internal use only */ |
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unsigned int res1; |
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unsigned int res2; |
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unsigned int res3; |
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} nvmlPciInfo_t; |
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enum nvmlEnableState_t { |
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NVML_FEATURE_DISABLED = 0, |
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NVML_FEATURE_ENABLED = 1, |
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NVML_FEATURE_UNKNOWN = 2 |
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}; |
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enum nvmlRestrictedAPI_t { |
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NVML_RESTRICTED_API_SET_APPLICATION_CLOCKS = 0, |
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NVML_RESTRICTED_API_SET_AUTO_BOOSTED_CLOCKS = 1, // not for GTX cards |
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NVML_RESTRICTED_API_COUNT = 2 |
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}; |
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enum nvmlReturn_t { |
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NVML_SUCCESS = 0, |
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NVML_ERROR_UNINITIALIZED = 1, |
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NVML_ERROR_INVALID_ARGUMENT = 2, |
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NVML_ERROR_NOT_SUPPORTED = 3, |
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NVML_ERROR_NO_PERMISSION = 4, |
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NVML_ERROR_ALREADY_INITIALIZED = 5, |
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NVML_ERROR_NOT_FOUND = 6, |
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NVML_ERROR_INSUFFICIENT_SIZE = 7, |
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NVML_ERROR_INSUFFICIENT_POWER = 8, |
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NVML_ERROR_DRIVER_NOT_LOADED = 9, |
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NVML_ERROR_TIMEOUT = 10, |
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NVML_ERROR_IRQ_ISSUE = 11, |
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NVML_ERROR_LIBRARY_NOT_FOUND = 12, |
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NVML_ERROR_FUNCTION_NOT_FOUND = 13, |
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NVML_ERROR_CORRUPTED_INFOROM = 14, |
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NVML_ERROR_GPU_IS_LOST = 15, |
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NVML_ERROR_RESET_REQUIRED = 16, |
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NVML_ERROR_OPERATING_SYSTEM = 17, |
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NVML_ERROR_LIB_RM_VERSION_MISMATCH = 18, |
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NVML_ERROR_IN_USE = 19, |
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NVML_ERROR_UNKNOWN = 999 |
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}; |
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enum nvmlClockType_t { |
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NVML_CLOCK_GRAPHICS = 0, |
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NVML_CLOCK_SM = 1, |
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NVML_CLOCK_MEM = 2, |
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NVML_CLOCK_VIDEO = 3, |
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NVML_CLOCK_COUNT |
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}; |
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enum nvmlClockId_t { |
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NVML_CLOCK_ID_CURRENT = 0, |
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NVML_CLOCK_ID_APP_CLOCK_TARGET = 1, |
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NVML_CLOCK_ID_APP_CLOCK_DEFAULT = 2, |
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NVML_CLOCK_ID_CUSTOMER_BOOST_MAX = 3, |
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NVML_CLOCK_ID_COUNT |
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}; |
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enum nvmlPcieUtilCounter_t { |
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NVML_PCIE_UTIL_TX_BYTES = 0, |
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NVML_PCIE_UTIL_RX_BYTES = 1, |
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NVML_PCIE_UTIL_COUNT |
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}; |
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enum nvmlValueType_t { |
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NVML_VALUE_TYPE_DOUBLE = 0, |
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NVML_VALUE_TYPE_UNSIGNED_INT = 1, |
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NVML_VALUE_TYPE_UNSIGNED_LONG = 2, |
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NVML_VALUE_TYPE_UNSIGNED_LONG_LONG = 3, |
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NVML_VALUE_TYPE_COUNT |
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}; |
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typedef int nvmlGpuTopologyLevel_t; |
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typedef int nvmlNvLinkCapability_t; |
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typedef int nvmlNvLinkErrorCounter_t; |
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typedef int nvmlNvLinkUtilizationControl_t; |
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#define NVML_DEVICE_SERIAL_BUFFER_SIZE 30 |
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#define NVML_DEVICE_UUID_BUFFER_SIZE 80 |
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#define NVML_DEVICE_VBIOS_VERSION_BUFFER_SIZE 32 |
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/* |
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* Handle to hold the function pointers for the entry points we need, |
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* and the shared library itself. |
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*/ |
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typedef struct { |
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void *nvml_dll; |
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int nvml_gpucount; |
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int cuda_gpucount; |
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unsigned int *nvml_pci_domain_id; |
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unsigned int *nvml_pci_bus_id; |
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unsigned int *nvml_pci_device_id; |
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unsigned int *nvml_pci_vendor_id; |
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unsigned int *nvml_pci_subsys_id; |
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int *nvml_cuda_device_id; /* map NVML dev to CUDA dev */ |
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int *cuda_nvml_device_id; /* map CUDA dev to NVML dev */ |
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nvmlDevice_t *devs; |
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nvmlEnableState_t *app_clocks; |
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nvmlReturn_t (*nvmlInit)(void); |
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nvmlReturn_t (*nvmlDeviceGetCount)(int *); |
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nvmlReturn_t (*nvmlDeviceGetHandleByIndex)(int, nvmlDevice_t *); |
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nvmlReturn_t (*nvmlDeviceGetAPIRestriction)(nvmlDevice_t, nvmlRestrictedAPI_t, nvmlEnableState_t *); |
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nvmlReturn_t (*nvmlDeviceSetAPIRestriction)(nvmlDevice_t, nvmlRestrictedAPI_t, nvmlEnableState_t); |
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nvmlReturn_t (*nvmlDeviceGetDefaultApplicationsClock)(nvmlDevice_t, nvmlClockType_t, unsigned int *); |
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nvmlReturn_t (*nvmlDeviceGetApplicationsClock)(nvmlDevice_t, nvmlClockType_t, unsigned int *); |
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nvmlReturn_t (*nvmlDeviceSetApplicationsClocks)(nvmlDevice_t, unsigned int, unsigned int); |
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nvmlReturn_t (*nvmlDeviceResetApplicationsClocks)(nvmlDevice_t); |
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nvmlReturn_t (*nvmlDeviceGetSupportedGraphicsClocks)(nvmlDevice_t, uint32_t mem, uint32_t *num, uint32_t *arr); |
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nvmlReturn_t (*nvmlDeviceGetSupportedMemoryClocks)(nvmlDevice_t, unsigned int *count, unsigned int *clocksMHz); |
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nvmlReturn_t (*nvmlDeviceGetClockInfo)(nvmlDevice_t, nvmlClockType_t, unsigned int *); |
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nvmlReturn_t (*nvmlDeviceGetMaxClockInfo)(nvmlDevice_t, nvmlClockType_t, unsigned int *); |
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nvmlReturn_t (*nvmlDeviceGetPowerManagementDefaultLimit)(nvmlDevice_t, unsigned int *limit); |
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nvmlReturn_t (*nvmlDeviceGetPowerManagementLimit)(nvmlDevice_t, unsigned int *limit); |
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nvmlReturn_t (*nvmlDeviceGetPowerManagementLimitConstraints)(nvmlDevice_t, unsigned int *min, unsigned int *max); |
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nvmlReturn_t (*nvmlDeviceSetPowerManagementLimit)(nvmlDevice_t device, unsigned int limit); |
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nvmlReturn_t (*nvmlDeviceGetPciInfo)(nvmlDevice_t, nvmlPciInfo_t *); |
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nvmlReturn_t (*nvmlDeviceGetCurrPcieLinkGeneration)(nvmlDevice_t device, unsigned int *gen); |
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nvmlReturn_t (*nvmlDeviceGetCurrPcieLinkWidth)(nvmlDevice_t device, unsigned int *width); |
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nvmlReturn_t (*nvmlDeviceGetMaxPcieLinkGeneration)(nvmlDevice_t device, unsigned int *gen); |
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nvmlReturn_t (*nvmlDeviceGetMaxPcieLinkWidth)(nvmlDevice_t device, unsigned int *width); |
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nvmlReturn_t (*nvmlDeviceGetName)(nvmlDevice_t, char *, int); |
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nvmlReturn_t (*nvmlDeviceGetTemperature)(nvmlDevice_t, int, unsigned int *); |
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nvmlReturn_t (*nvmlDeviceGetFanSpeed)(nvmlDevice_t, unsigned int *); |
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nvmlReturn_t (*nvmlDeviceGetPerformanceState)(nvmlDevice_t, int *); /* enum */ |
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nvmlReturn_t (*nvmlDeviceGetPowerUsage)(nvmlDevice_t, unsigned int *); |
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nvmlReturn_t (*nvmlDeviceGetSerial)(nvmlDevice_t, char *serial, unsigned int len); |
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nvmlReturn_t (*nvmlDeviceGetUUID)(nvmlDevice_t, char *uuid, unsigned int len); |
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nvmlReturn_t (*nvmlDeviceGetVbiosVersion)(nvmlDevice_t, char *version, unsigned int len); |
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nvmlReturn_t (*nvmlSystemGetDriverVersion)(char *version, unsigned int len); |
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char* (*nvmlErrorString)(nvmlReturn_t); |
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nvmlReturn_t (*nvmlShutdown)(void); |
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// v331 |
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nvmlReturn_t (*nvmlDeviceGetEnforcedPowerLimit)(nvmlDevice_t, unsigned int *limit); |
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// v340 |
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#ifdef __linux__ |
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nvmlReturn_t (*nvmlDeviceClearCpuAffinity)(nvmlDevice_t); |
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nvmlReturn_t (*nvmlDeviceGetCpuAffinity)(nvmlDevice_t, unsigned int cpuSetSize, unsigned long* cpuSet); |
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nvmlReturn_t (*nvmlDeviceSetCpuAffinity)(nvmlDevice_t); |
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#endif |
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// v346 |
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nvmlReturn_t (*nvmlDeviceGetPcieThroughput)(nvmlDevice_t, nvmlPcieUtilCounter_t, unsigned int *value); |
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// v36x (API 8) |
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nvmlReturn_t (*nvmlDeviceGetClock)(nvmlDevice_t, nvmlClockType_t clockType, nvmlClockId_t clockId, unsigned int *clockMHz); |
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#ifdef __linux__ |
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nvmlReturn_t (*nvmlSystemGetTopologyGpuSet)(unsigned int cpuNumber, unsigned int *count, nvmlDevice_t *deviceArray); |
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nvmlReturn_t (*nvmlDeviceGetTopologyNearestGpus)(nvmlDevice_t, nvmlGpuTopologyLevel_t level, unsigned int *count, nvmlDevice_t *deviceArray); |
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nvmlReturn_t (*nvmlDeviceGetTopologyCommonAncestor)(nvmlDevice_t device1, nvmlDevice_t device2, nvmlGpuTopologyLevel_t *pathInfo); |
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#endif |
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nvmlReturn_t (*nvmlDeviceGetNvLinkState)(nvmlDevice_t, unsigned int link, nvmlEnableState_t *isActive); |
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nvmlReturn_t (*nvmlDeviceGetNvLinkVersion)(nvmlDevice_t, unsigned int link, unsigned int *version); |
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nvmlReturn_t (*nvmlDeviceGetNvLinkCapability)(nvmlDevice_t, unsigned int link, nvmlNvLinkCapability_t capability, unsigned int *capResult); |
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nvmlReturn_t (*nvmlDeviceGetNvLinkRemotePciInfo)(nvmlDevice_t, unsigned int link, nvmlPciInfo_t *pci); |
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nvmlReturn_t (*nvmlDeviceGetNvLinkErrorCounter)(nvmlDevice_t, unsigned int link, nvmlNvLinkErrorCounter_t counter, unsigned long long *counterValue); |
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nvmlReturn_t (*nvmlDeviceResetNvLinkErrorCounters)(nvmlDevice_t, unsigned int link); |
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nvmlReturn_t (*nvmlDeviceSetNvLinkUtilizationControl)(nvmlDevice_t, unsigned int link, unsigned int counter, nvmlNvLinkUtilizationControl_t *control, unsigned int reset); |
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nvmlReturn_t (*nvmlDeviceGetNvLinkUtilizationControl)(nvmlDevice_t, unsigned int link, unsigned int counter, nvmlNvLinkUtilizationControl_t *control); |
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nvmlReturn_t (*nvmlDeviceGetNvLinkUtilizationCounter)(nvmlDevice_t, unsigned int link, unsigned int counter, unsigned long long *rxcounter, unsigned long long *txcounter); |
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nvmlReturn_t (*nvmlDeviceFreezeNvLinkUtilizationCounter)(nvmlDevice_t, unsigned int link, unsigned int counter, nvmlEnableState_t freeze); |
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nvmlReturn_t (*nvmlDeviceResetNvLinkUtilizationCounter)(nvmlDevice_t, unsigned int link, unsigned int counter); |
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} nvml_handle; |
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nvml_handle * nvml_create(); |
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int nvml_destroy(nvml_handle *nvmlh); |
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// Debug informations |
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void nvml_print_device_info(int dev_id); |
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// Query the number of GPUs seen by NVML |
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int nvml_get_gpucount(nvml_handle *nvmlh, int *gpucount); |
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int nvml_set_plimit(nvml_handle *nvmlh, int dev_id); |
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int nvml_set_pstate(nvml_handle *nvmlh, int dev_id); |
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int nvml_set_clocks(nvml_handle *nvmlh, int dev_id); |
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int nvml_reset_clocks(nvml_handle *nvmlh, int dev_id); |
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/* api functions */ |
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unsigned int gpu_fanpercent(struct cgpu_info *gpu); |
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unsigned int gpu_fanrpm(struct cgpu_info *gpu); |
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float gpu_temp(struct cgpu_info *gpu); |
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unsigned int gpu_power(struct cgpu_info *gpu); |
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unsigned int gpu_plimit(struct cgpu_info *gpu); |
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int gpu_pstate(struct cgpu_info *gpu); |
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int gpu_busid(struct cgpu_info *gpu); |
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// pid/vid, sn and bios rev |
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int gpu_info(struct cgpu_info *gpu); |
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int gpu_vendor(uint8_t pci_bus_id, char *vendorname); |
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/* nvapi functions */ |
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#ifdef WIN32 |
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int nvapi_init(); |
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int nvapi_init_settings(); |
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// to debug nvapi.. |
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int nvapi_pstateinfo(unsigned int devNum); |
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uint8_t nvapi_get_plimit(unsigned int devNum); |
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// nvapi devNum from dev_id (cuda GPU #N) |
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unsigned int nvapi_devnum(int dev_id); |
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int nvapi_devid(unsigned int devNum); |
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void nvapi_toggle_clocks(int thr_id, bool enable); |
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// cuda Replacement for 6.5 compat |
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int nvapiMemGetInfo(int dev_id, uint64_t *free, uint64_t *total); |
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#endif |
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#endif /* USE_WRAPNVML */ |
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void gpu_led_on(int dev_id); |
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void gpu_led_percent(int dev_id, int percent); |
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void gpu_led_off(int dev_id); |
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#define LED_MODE_OFF 0 |
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#define LED_MODE_SHARES 1 |
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#define LED_MODE_MINING 2 |
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/* ------ nvidia-settings stuff for linux -------------------- */ |
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int nvs_init(); |
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int nvs_set_clocks(int dev_id); |
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void nvs_reset_clocks(int dev_id); |
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// nvidia-settings (X) devNum from dev_id (cuda GPU #N) |
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int8_t nvs_devnum(int dev_id); |
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int nvs_devid(int8_t devNum); |
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extern bool need_nvsettings; |
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