nvml: add new getclock api (v8)
+ some new functions to test on pascal (if supported)
This commit is contained in:
Tanguy Pruvot
parent
fe99de24a8
commit
fd757f2180
3
cuda.cpp
3
cuda.cpp
@ -106,6 +106,9 @@ void cuda_print_devices()
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cudaGetDeviceProperties(&props, dev_id);
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if (!opt_n_threads || n < opt_n_threads) {
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fprintf(stderr, "GPU #%d: SM %d.%d %s\n", dev_id, props.major, props.minor, device_name[dev_id]);
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#ifdef USE_WRAPNVML
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if (opt_debug) nvml_print_device_info(dev_id);
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#endif
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}
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}
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}
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60
nvml.cpp
60
nvml.cpp
@ -188,6 +188,14 @@ nvml_handle * nvml_create()
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nvmlh->nvmlDeviceGetEnforcedPowerLimit = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int *limit))
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wrap_dlsym(nvmlh->nvml_dll, "nvmlDeviceGetEnforcedPowerLimit");
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// v340
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#ifdef __linux__
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nvmlh->nvmlDeviceClearCpuAffinity = (nvmlReturn_t (*)(nvmlDevice_t))
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wrap_dlsym(nvmlh->nvml_dll, "nvmlDeviceClearCpuAffinity");
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nvmlh->nvmlDeviceGetCpuAffinity = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int sz, unsigned long *cpuSet))
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wrap_dlsym(nvmlh->nvml_dll, "nvmlDeviceGetCpuAffinity");
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nvmlh->nvmlDeviceSetCpuAffinity = (nvmlReturn_t (*)(nvmlDevice_t))
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wrap_dlsym(nvmlh->nvml_dll, "nvmlDeviceSetCpuAffinity");
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#endif
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/* NVML_ERROR_NOT_SUPPORTED
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nvmlh->nvmlDeviceGetAutoBoostedClocksEnabled = (nvmlReturn_t (*)(nvmlDevice_t, nvmlEnableState_t *isEnabled, nvmlEnableState_t *defaultIsEnabled))
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wrap_dlsym(nvmlh->nvml_dll, "nvmlDeviceGetAutoBoostedClocksEnabled");
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@ -196,6 +204,11 @@ nvml_handle * nvml_create()
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// v346
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nvmlh->nvmlDeviceGetPcieThroughput = (nvmlReturn_t (*)(nvmlDevice_t, nvmlPcieUtilCounter_t, unsigned int *value))
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wrap_dlsym(nvmlh->nvml_dll, "nvmlDeviceGetPcieThroughput");
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// v36x (API 8 / Pascal)
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nvmlh->nvmlDeviceGetClock = (nvmlReturn_t (*)(nvmlDevice_t, nvmlClockType_t clockType, nvmlClockId_t clockId, unsigned int *clockMHz))
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wrap_dlsym(nvmlh->nvml_dll, "nvmlDeviceGetClock");
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nvmlh->nvmlDeviceGetMaxCustomerBoostClock = (nvmlReturn_t (*)(nvmlDevice_t, nvmlClockType_t clockType, unsigned int *clockMHz))
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wrap_dlsym(nvmlh->nvml_dll, "nvmlDeviceGetMaxCustomerBoostClock");
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if (nvmlh->nvmlInit == NULL ||
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nvmlh->nvmlShutdown == NULL ||
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@ -528,6 +541,53 @@ int nvml_set_plimit(nvml_handle *nvmlh, int dev_id)
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return 1;
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}
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// ccminer -D -n
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#define LSTDEV_PFX " "
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void nvml_print_device_info(int dev_id)
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{
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if (!hnvml) return;
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int n = hnvml->cuda_nvml_device_id[dev_id];
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if (n < 0 || n >= hnvml->nvml_gpucount)
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return;
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nvmlReturn_t rc;
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if (hnvml->nvmlDeviceGetClock) {
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uint32_t gpu_clk = 0, mem_clk = 0;
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fprintf(stderr, "------- Clocks -------\n");
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hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_GRAPHICS, NVML_CLOCK_ID_APP_CLOCK_DEFAULT, &gpu_clk);
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rc = hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_MEM, NVML_CLOCK_ID_APP_CLOCK_DEFAULT, &mem_clk);
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if (rc == NVML_SUCCESS) {
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fprintf(stderr, LSTDEV_PFX "DEFAULT MEM %4u GPU %4u MHz\n", mem_clk, gpu_clk);
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}
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hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_GRAPHICS, NVML_CLOCK_ID_APP_CLOCK_TARGET, &gpu_clk);
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rc = hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_MEM, NVML_CLOCK_ID_APP_CLOCK_TARGET, &mem_clk);
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if (rc == NVML_SUCCESS) {
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fprintf(stderr, LSTDEV_PFX "TARGET MEM %4u GPU %4u MHz\n", mem_clk, gpu_clk);
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}
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hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_GRAPHICS, NVML_CLOCK_ID_CURRENT, &gpu_clk);
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rc = hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_MEM, NVML_CLOCK_ID_CURRENT, &mem_clk);
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if (rc == NVML_SUCCESS) {
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fprintf(stderr, LSTDEV_PFX "CURRENT MEM %4u GPU %4u MHz\n", mem_clk, gpu_clk);
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}
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// NVML_ERROR_NOT_SUPPORTED on Maxwell (361.62)
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hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_GRAPHICS, NVML_CLOCK_ID_CUSTOMER_BOOST_MAX, &gpu_clk);
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rc = hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_MEM, NVML_CLOCK_ID_CUSTOMER_BOOST_MAX, &mem_clk);
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if (rc == NVML_SUCCESS) {
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fprintf(stderr, LSTDEV_PFX "BOOSTED MEM %4u GPU %4u MHz\n", mem_clk, gpu_clk);
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}
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// NVML_ERROR_NOT_SUPPORTED on Maxwell (361.62)
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hnvml->nvmlDeviceGetMaxCustomerBoostClock(hnvml->devs[n], NVML_CLOCK_GRAPHICS, &gpu_clk);
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rc = hnvml->nvmlDeviceGetMaxCustomerBoostClock(hnvml->devs[n], NVML_CLOCK_MEM, &mem_clk);
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if (rc == NVML_SUCCESS) {
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fprintf(stderr, LSTDEV_PFX "MXBOOST MEM %4u GPU %4u MHz\n", mem_clk, gpu_clk);
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}
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}
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}
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int nvml_get_gpucount(nvml_handle *nvmlh, int *gpucount)
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{
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*gpucount = nvmlh->nvml_gpucount;
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68
nvml.h
68
nvml.h
@ -57,13 +57,32 @@ enum nvmlReturn_t {
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NVML_ERROR_INSUFFICIENT_POWER = 8,
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NVML_ERROR_DRIVER_NOT_LOADED = 9,
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NVML_ERROR_TIMEOUT = 10,
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NVML_ERROR_IRQ_ISSUE = 11,
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NVML_ERROR_LIBRARY_NOT_FOUND = 12,
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NVML_ERROR_FUNCTION_NOT_FOUND = 13,
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NVML_ERROR_CORRUPTED_INFOROM = 14,
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NVML_ERROR_GPU_IS_LOST = 15,
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NVML_ERROR_RESET_REQUIRED = 16,
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NVML_ERROR_OPERATING_SYSTEM = 17,
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NVML_ERROR_LIB_RM_VERSION_MISMATCH = 18,
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NVML_ERROR_IN_USE = 19,
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NVML_ERROR_UNKNOWN = 999
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};
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enum nvmlClockType_t {
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NVML_CLOCK_GRAPHICS = 0,
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NVML_CLOCK_SM = 1,
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NVML_CLOCK_MEM = 2
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NVML_CLOCK_MEM = 2,
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NVML_CLOCK_VIDEO = 3,
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NVML_CLOCK_COUNT
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};
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enum nvmlClockId_t {
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NVML_CLOCK_ID_CURRENT = 0,
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NVML_CLOCK_ID_APP_CLOCK_TARGET = 1,
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NVML_CLOCK_ID_APP_CLOCK_DEFAULT = 2,
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NVML_CLOCK_ID_CUSTOMER_BOOST_MAX = 3,
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NVML_CLOCK_ID_COUNT
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};
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enum nvmlPcieUtilCounter_t {
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@ -80,6 +99,11 @@ enum nvmlValueType_t {
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NVML_VALUE_TYPE_COUNT
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};
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typedef int nvmlGpuTopologyLevel_t;
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typedef int nvmlNvLinkCapability_t;
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typedef int nvmlNvLinkErrorCounter_t;
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typedef int nvmlNvLinkUtilizationControl_t;
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#define NVML_DEVICE_SERIAL_BUFFER_SIZE 30
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#define NVML_DEVICE_UUID_BUFFER_SIZE 80
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#define NVML_DEVICE_VBIOS_VERSION_BUFFER_SIZE 32
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@ -136,21 +160,44 @@ typedef struct {
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// v331
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nvmlReturn_t (*nvmlDeviceGetEnforcedPowerLimit)(nvmlDevice_t, unsigned int *limit);
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// v340
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//nvmlReturn_t (*nvmlDeviceGetCpuAffinity)(nvmlDevice_t, unsigned int cpuSetSize, unsigned long* cpuSet);
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//nvmlReturn_t (*nvmlDeviceSetCpuAffinity)(nvmlDevice_t);
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//nvmlReturn_t (*nvmlDeviceGetAutoBoostedClocksEnabled)(nvmlDevice_t, nvmlEnableState_t *isEnabled, nvmlEnableState_t *defaultIsEnabled);
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//nvmlReturn_t (*nvmlDeviceSetAutoBoostedClocksEnabled)(nvmlDevice_t, nvmlEnableState_t enabled);
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#ifdef __linux__
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nvmlReturn_t (*nvmlDeviceClearCpuAffinity)(nvmlDevice_t);
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nvmlReturn_t (*nvmlDeviceGetCpuAffinity)(nvmlDevice_t, unsigned int cpuSetSize, unsigned long* cpuSet);
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nvmlReturn_t (*nvmlDeviceSetCpuAffinity)(nvmlDevice_t);
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#endif
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nvmlReturn_t (*nvmlDeviceGetAutoBoostedClocksEnabled)(nvmlDevice_t, nvmlEnableState_t *isEnabled, nvmlEnableState_t *defaultIsEnabled);
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nvmlReturn_t (*nvmlDeviceSetAutoBoostedClocksEnabled)(nvmlDevice_t, nvmlEnableState_t enabled);
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// v346
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nvmlReturn_t (*nvmlDeviceGetPcieThroughput)(nvmlDevice_t, nvmlPcieUtilCounter_t, unsigned int *value);
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} nvml_handle;
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// v36x (API 8)
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nvmlReturn_t (*nvmlDeviceGetClock)(nvmlDevice_t, nvmlClockType_t clockType, nvmlClockId_t clockId, unsigned int *clockMHz);
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nvmlReturn_t (*nvmlDeviceGetMaxCustomerBoostClock)(nvmlDevice_t, nvmlClockType_t clockType, unsigned int *clockMHz);
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#ifdef __linux__
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nvmlReturn_t (*nvmlSystemGetTopologyGpuSet)(unsigned int cpuNumber, unsigned int *count, nvmlDevice_t *deviceArray);
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nvmlReturn_t (*nvmlDeviceGetTopologyNearestGpus)(nvmlDevice_t, nvmlGpuTopologyLevel_t level, unsigned int *count, nvmlDevice_t *deviceArray);
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nvmlReturn_t (*nvmlDeviceGetTopologyCommonAncestor)(nvmlDevice_t device1, nvmlDevice_t device2, nvmlGpuTopologyLevel_t *pathInfo);
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#endif
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nvmlReturn_t (*nvmlDeviceGetNvLinkState)(nvmlDevice_t, unsigned int link, nvmlEnableState_t *isActive);
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nvmlReturn_t (*nvmlDeviceGetNvLinkVersion)(nvmlDevice_t, unsigned int link, unsigned int *version);
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nvmlReturn_t (*nvmlDeviceGetNvLinkCapability)(nvmlDevice_t, unsigned int link, nvmlNvLinkCapability_t capability, unsigned int *capResult);
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nvmlReturn_t (*nvmlDeviceGetNvLinkRemotePciInfo)(nvmlDevice_t, unsigned int link, nvmlPciInfo_t *pci);
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nvmlReturn_t (*nvmlDeviceGetNvLinkErrorCounter)(nvmlDevice_t, unsigned int link, nvmlNvLinkErrorCounter_t counter, unsigned long long *counterValue);
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nvmlReturn_t (*nvmlDeviceResetNvLinkErrorCounters)(nvmlDevice_t, unsigned int link);
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nvmlReturn_t (*nvmlDeviceSetNvLinkUtilizationControl)(nvmlDevice_t, unsigned int link, unsigned int counter, nvmlNvLinkUtilizationControl_t *control, unsigned int reset);
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nvmlReturn_t (*nvmlDeviceGetNvLinkUtilizationControl)(nvmlDevice_t, unsigned int link, unsigned int counter, nvmlNvLinkUtilizationControl_t *control);
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nvmlReturn_t (*nvmlDeviceGetNvLinkUtilizationCounter)(nvmlDevice_t, unsigned int link, unsigned int counter, unsigned long long *rxcounter, unsigned long long *txcounter);
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nvmlReturn_t (*nvmlDeviceFreezeNvLinkUtilizationCounter)(nvmlDevice_t, unsigned int link, unsigned int counter, nvmlEnableState_t freeze);
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nvmlReturn_t (*nvmlDeviceResetNvLinkUtilizationCounter)(nvmlDevice_t, unsigned int link, unsigned int counter);
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} nvml_handle;
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nvml_handle * nvml_create();
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int nvml_destroy(nvml_handle *nvmlh);
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/*
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* Query the number of GPUs seen by NVML
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*/
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// Debug informations
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void nvml_print_device_info(int dev_id);
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// Query the number of GPUs seen by NVML
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int nvml_get_gpucount(nvml_handle *nvmlh, int *gpucount);
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int nvml_set_plimit(nvml_handle *nvmlh, int dev_id);
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@ -168,8 +215,9 @@ unsigned int gpu_power(struct cgpu_info *gpu);
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int gpu_pstate(struct cgpu_info *gpu);
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int gpu_busid(struct cgpu_info *gpu);
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/* pid/vid, sn and bios rev */
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// pid/vid, sn and bios rev
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int gpu_info(struct cgpu_info *gpu);
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int gpu_vendor(uint8_t pci_bus_id, char *vendorname);
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