nvml: allow to keep modified clocks + vendors

--keep-clocks option prevent reset clocks on exit...

README.txt

@@ -135,6 +135,9 @@ its command line interface and options.
       --max-temp=N      Only mine if gpu temp is less than specified value
       --max-rate=N[KMG] Only mine if net hashrate is less than specified value
       --max-diff=N      Only mine if net difficulty is less than specified value
+      --pstate=0        will force the Geforce 9xx to run in P0 P-State
+      --plimit=150W     set the gpu power limit, allow multiple values for N cards
+      --keep-clocks     prevent reset clocks and/or power limit on exit
   -B, --background      run the miner in the background
       --benchmark       run in offline benchmark mode
       --cputest         debug hashes from cpu algorithms

ccminer.cpp

@@ -200,6 +200,7 @@ uint32_t device_gpu_clocks[MAX_GPUS] = { 0 };
 uint32_t device_mem_clocks[MAX_GPUS] = { 0 };
 uint32_t device_plimit[MAX_GPUS] = { 0 };
 int8_t device_pstate[MAX_GPUS] = { -1 };
+static bool opt_keep_clocks = false;
 
 // un-linked to cmdline scrypt options (useless)
 int device_batchsize[MAX_GPUS] = { 0 };
@@ -416,6 +417,7 @@ struct option options[] = {
 	{ "mem-clock", 1, NULL, 1071 },
 	{ "pstate", 1, NULL, 1072 },
 	{ "plimit", 1, NULL, 1073 },
+	{ "keep-clocks", 0, NULL, 1074 },
 #ifdef HAVE_SYSLOG_H
 	{ "syslog", 0, NULL, 'S' },
 	{ "syslog-prefix", 1, NULL, 1018 },
@@ -539,7 +541,7 @@ void proper_exit(int reason)
 	timeEndPeriod(1); // else never executed
 #endif
 #ifdef USE_WRAPNVML
-	if (hnvml) {
+	if (hnvml && !opt_keep_clocks) {
 		for (int n=0; n < opt_n_threads; n++) {
 			nvml_reset_clocks(hnvml, device_map[n]);
 		}
@@ -2759,6 +2761,9 @@ void parse_arg(int key, char *arg)
 			}
 		}
 		break;
+	case 1074: /* --keep-clocks */
+		opt_keep_clocks = true;
+		break;
 	case 1005:
 		opt_benchmark = true;
 		want_longpoll = false;

nvml.cpp

@@ -365,9 +365,10 @@ int nvml_set_clocks(nvml_handle *nvmlh, int dev_id)
 	return 1;
 }
 
-/* reset default app clocks to an used device */
+/* reset default app clocks and limits on exit */
 int nvml_reset_clocks(nvml_handle *nvmlh, int dev_id)
 {
+	int ret = 0;
 	nvmlReturn_t rc;
 	uint32_t gpu_clk = 0, mem_clk = 0;
 	int n = nvmlh->cuda_nvml_device_id[dev_id];
@@ -378,9 +379,9 @@ int nvml_reset_clocks(nvml_handle *nvmlh, int dev_id)
 		rc = nvmlh->nvmlDeviceResetApplicationsClocks(nvmlh->devs[n]);
 		if (rc != NVML_SUCCESS) {
 			applog(LOG_WARNING, "GPU #%d: unable to reset application clocks", dev_id);
-			return -1;
 		}
 		gpu_clocks_changed[dev_id] = 0;
+		ret = 1;
 	}
 
 	if (gpu_limits_changed[dev_id]) {
@@ -391,9 +392,9 @@ int nvml_reset_clocks(nvml_handle *nvmlh, int dev_id)
 				nvmlh->nvmlDeviceSetPowerManagementLimit(nvmlh->devs[n], plimit);
 		}
 		gpu_limits_changed[dev_id] = 0;
-		return 1;
+		ret = 1;
 	}
-	return 0;
+	return ret;
 }
 
 
@@ -511,8 +512,7 @@ int nvml_set_plimit(nvml_handle *nvmlh, int dev_id)
 	}
 
 	gpu_limits_changed[dev_id] = 1;
-
+	return 1;
-	return 0;
 }
 
 int nvml_get_gpucount(nvml_handle *nvmlh, int *gpucount)
@@ -1066,12 +1066,20 @@ static int translate_vendor_id(uint16_t vid, char *vendorname)
 		const char *name;
 	} vendors[] = {
 		{ 0x1043, "ASUS" },
+		{ 0x107D, "Leadtek" },
 		{ 0x10B0, "Gainward" },
 		// { 0x10DE, "NVIDIA" },
 		{ 0x1458, "Gigabyte" },
 		{ 0x1462, "MSI" },
+		{ 0x154B, "PNY" },
+		{ 0x1682, "XFX" },
+		{ 0x196D, "Club3D" },
 		{ 0x19DA, "Zotac" },
+		{ 0x19F1, "BFG" },
+		{ 0x1ACC, "PoV" },
+		{ 0x1B4C, "KFA2" },
 		{ 0x3842, "EVGA" },
+		{ 0x7377, "Colorful" },
 		{ 0, "" }
 	};